74F193SJ 반도체 회로 부품 판매점
Up/Down Binary Counter with Separate Up/Down Clocks
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 Fairchild |
April 1988
Revised July 1999
74F193
Up/Down Binary Counter with Separate Up/Down Clocks
General Description
The 74F193 is an up/down modulo-16 binary counter. Sep-
arate Count Up and Count Down Clocks are used, and in
either counting mode the circuits operate synchronously.
The outputs change state synchronously with the LOW-to-
HIGH transitions on the clock inputs. Separate Terminal
Count Up and Terminal Count Down outputs are provided
that are used as the clocks for subsequent stages without
extra logic, thus simplifying multi-stage counter designs.
Individual preset inputs allow the circuit to be used as a
programmable counter. Both the Parallel Load (PL) and the
Master Reset (MR) inputs asynchronously override the
clocks.
Ordering Code:
Order Number Package Number
Package Description
74F193SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74F193SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F193PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009497
www.fairchildsemi.com
Unit Loading/Fan Out
Pin Names
Description
CPU
CPD
MR
PL
P0–P3
Q0–Q3
TCD
TCU
Count Up Clock Input (Active Rising Edge)
Count Down Clock Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Asynchronous Parallel Load Input (Active LOW)
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count Down (Borrow) Output (Active LOW)
Terminal Count Up (Carry) Output (Active LOW)
U.L.
HIGH/LOW
1.0/3.0
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−1.8 mA
20 µA/−1.8 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
The 74F193 is a 4-bit binary synchronous up/down (revers-
ible) counter. It contains four edge-triggered flip-flops, with
internal gating and steering logic to provide master reset,
individual preset, count up and count down operations.
A LOW-to-HIGH transition on the CP input to each flip-flop
causes the output to change state. Synchronous switching,
as opposed to ripple counting, is achieved by driving the
steering gates of all stages from a common Count Up line
and a common Count Down line, thereby causing all state
changes to be initiated simultaneously. A LOW-to-HIGH
transition on the Count Up input will advance the count by
one; a similar transition on the Count Down input will
decrease the count by one. While counting with one clock
input, the other should be held HIGH, as indicated in the
Function Table.
The Terminal Count Up (TCU) and Terminal Count Down
(TCD) outputs are normally HIGH. When the circuit has
reached the maximum count state 15, the next HIGH-to-
LOW transition of the Count Up Clock will cause TCU to go
LOW. TCU will stay LOW until CPU goes HIGH again, thus
effectively repeating the Count Up Clock, but delayed by
two gate delays. Similarly, the TCD output will go LOW
when the circuit is in the zero state and the Count Down
Clock goes LOW. Since the TC outputs repeat the clock
waveforms, they can be used as the clock input signals to
the next higher order circuit in a multistage counter.
TCU = Q0 • Q1 • Q2 • Q3 • CPU
TCD = Q0• Q1 • Q2 • Q3 • CPD
The 74F193 has an asynchronous parallel load capability
permitting the counter to be preset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW, informa-
tion present on the Parallel Data input (P0–P3) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs. A HIGH signal on the
Master Reset input will disable the preset gates, override
both clock inputs, and latch each Q output in the LOW
state. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of
that clock will be interpreted as a legitimate signal and will
be counted.
Function Table
MR PL CPU CPD
Mode
H X X X Reset (Asyn.)
L L X X Preset (Asyn.)
L H H H No Change
L H
H Count Up
L H H
Count Down
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
State Diagram
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관련 데이터시트
74F193SC
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