74F192PC 반도체 회로 부품 판매점
Up/Down Decade Counter with Separate Up/Down Clocks
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 National |
November 1994
54F 74F192
Up Down Decade Counter
with Separate Up Down Clocks
General Description
The ’F192 is an up down BCD decade (8421) counter Sep-
arate Count Up and Count Down Clocks are used and in
either counting mode the circuits operate synchronously
The outputs change state synchronously with the LOW-to-
HIGH transitions on the clock inputs
Separate Terminal Count Up and Terminal Count Down out-
puts are used as the clocks for a subsequent stage without
extra logic thus simplifying multistage counter designs Indi-
vidual preset inputs allow the circuit to be used as a pro-
grammable counter Both the Parallel Load (PL) and the
Master Reset (MR) inputs asynchronously override the
clocks
Features
Y Guaranteed 4000V minimum ESD protection
Commercial
74F192PC
74F192SC (Note 1)
74F192SJ (Note 1)
Military
54F192DM (Note 2)
54F192FM (Note 2)
54F192LM (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
IEEE IEC
TL F 9496–3
TL F 9496 – 1
TL F 9496 – 2
TL F 9496–6
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9496
RRD-B30M75 Printed in U S A
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L Input IIH IIL
HIGH LOW Output IOH IOL
CPU
CPD
MR
PL
P0 – P3
Q0 – Q3
TCD
TCU
Count Up Clock Input (Active Rising Edge)
Count Down Clock Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Asynchronous Parallel Load Input (Active LOW)
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count Down (Borrow) Output (Active LOW)
Terminal Count Up (Carry) Output (Active LOW)
10 30
10 30
10 10
10 10
10 10
50 33 3
50 33 3
50 33 3
20 mA b1 8 mA
20 mA b1 8 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
b1 mA 20 mA
Functional Description
The ’F192 is an asynchronously presettable decade coun-
ter It contains four edge-triggered flip-flops with internal
gating and steering logic to provide master reset individual
preset count up and count down operations
A LOW-to-HIGH transition on the CP input to each flip-flop
causes the output to change state Synchronous switching
as opposed to ripple counting is achieved by driving the
steering gates of all stages from a common Count Up line
and a common Count Down line thereby causing all state
changes to be initiated simultaneously A LOW-to-HIGH
transition on the Count Up input will advance the count by
one a similar transition on the Count Down input will de-
crease the count by one While counting with one clock in-
put the other should be held HIGH as indicated in the
Function Table Otherwise the circuit will either count by
twos or not at all depending on the state of the first flip-flop
which cannot toggle as long as either clock input is LOW
The Terminal Count Up (TCU) and Terminal Count Down
(TCD) outputs are normally HIGH When the circuit has
reached the maximum count state 9 the next HIGH-to-LOW
transition of the Count Up Clock will cause TCU to go LOW
TCU will stay LOW until CPU goes HIGH again thus effec-
tively repeating the Count Up Clock but delayed by two
gate delays Similarly the TCD output will go LOW when the
circuit is in the zero state and the Count Down Clock goes
LOW Since the TC outputs repeat the clock waveforms
they can be used as the clock input signals to the next
higher order circuit in a multistage counter
TCU e Q0 Q3 CPU
TCD e Q0 Q1 Q2 Q3 CPD
The ’F192 has an asynchronous parallel load capability per-
mitting the counter to be preset When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW informa-
tion present on the Parallel Data input (P0 – P3) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs A HIGH signal on the
Master Reset input will disable the preset gates override
both clock inputs and latch each Q output in the LOW state
If one of the clock inputs is LOW during and after a reset or
load operation the next LOW-to-HIGH transition of that
clock will be interpreted as a legitimate signal and will be
counted
Function Table
MR PL CPU CPD
HX
X
X
LL
X
X
LH H
H
L HL H
LH HL
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
Mode
Reset (Asyn )
Preset (Asyn )
No Change
Count Up
Count Down
State Diagram
TL F 9496 – 4
2
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74F192PC data
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
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전력반도체 문의 : 010-3582-2743
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