74F189 반도체 회로 부품 판매점
64-Bit Random Access Memory with 3-STATE Outputs
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 Fairchild |
April 1988
Revised July 1999
74F189
64-Bit Random Access Memory with 3-STATE Outputs
General Description
The F189 is a high-speed 64-bit RAM organized as a 16-
word by 4-bit array. Address inputs are buffered to mini-
mize loading and are fully decoded on-chip. The outputs
are 3-STATE and are in the high impedance state when-
ever the Chip Select (CS) input is HIGH. The outputs are
active only in the Read mode and the output data is the
complement of the stored data.
Features
s 3-STATE outputs for data bus applications
s Buffered inputs minimize loading
s Address decoding on-chip
s Diode clamped inputs minimize ringing
Ordering Code:
Order Number Package Number
Package Description
74F189SC
M16B
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74F189SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F189PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009493
www.fairchildsemi.com
Unit Loading/Fan Out
Pin Names
Description
U.L.
HIGH/LOW
Input IIH/IIL
Output IOH/IOL
A0–A3
CS
Address Inputs
Chip Select Input (Active LOW)
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−1.2 mA
WE Write Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
D0–D3
O 0–O 3
Data Inputs
Inverted Data Outputs
1.0/1.0
20 µA/−0.6 mA
150/40 (33.3) −3.0 mA/24 mA (20 mA)
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Inputs
CS WE
LL
LH
HX
Operation
Condition of Outputs
Write
Read
Inhibit
High Impedance
Complement of Stored Data
High Impedance
Block Diagram
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