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PDF ZL30406 Data sheet ( Hoja de datos )
| Número de pieza | ZL30406 | |
| Descripción | SONET/SDH Clock Multiplier PLL | |
| Fabricantes | Zarlink | |
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ZL30406
SONET/SDH Clock Multiplier PLL
Features
• Meets jitter requirements of Telcordia GR-253-
CORE for OC-48, OC-12, and OC-3 rates
• Meets jitter requirements of ITU-T G.813 for STM-
16, STM-4 and STM-1 rates
• Provides four LVPECL differential output clocks at
77.76 MHz
• Provides a CML differential clock programmable
to 19.44 MHz, 38.88 MHz, 77.76 MHz and
155.52 MHz
• Provides a single-ended CMOS clock at
19.44 MHz
• Provides enable/disable control of output clocks
• Accepts a CMOS reference at 19.44 MHz
• 3.3 V supply
Applications
• SONET/SDH line cards
• Network Element timing cards
Data Sheet
February 2005
Ordering Information
ZL30406QGC 64 Pin TQFP
ZL30406QGC1 64 Pin TQFP*
*Pb Free Matte Tin
-40°C to +85°C
Description
Trays
Trays
The ZL30406 is an analog phase-locked loop (APLL)
designed to provide rate conversion and jitter
attenuation for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30406 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1
rates and ITU-T G.813 STM-16, STM-4 and STM-1
rates.
The ZL30406 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 77.76 MHz, a CML differential
clock programmable to 19.44 MHz, 38.88 MHz,
77.76 MHz and 155.52 MHz and a single-ended
CMOS clock at 19.44 MHz. The output clocks can
be individually enabled or disabled.
C19i
BIAS
LPF
Frequency
& Phase
Detector
19.44MHz
Reference &
Bias circuit
Loop
Filter
VCO
C77oEN-A
C77oEN-B
OC-CLKoEN
C77o,C155o
C19o, C38o,
CML-P/N outputs
Output
Interface
Circuit
OC-CLKoP/N
C77oP/N-A
C77oP/N-B
C77oP/N-C
C77oP/N-D
C19o
VDD GND VCC
FS1-2
C19oEN
C77oEN-C
C77oEN-D
Figure 1 - Functional Block Diagram
15
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL30406
Data Sheet
1.0 Functional Description
The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for
SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the
ZL30406 is shown in Figure 1 and a brief description is presented in the following sections.
1.1 Frequency/Phase Detector
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback
signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase
difference between the two. This error signal is passed to the Loop Filter circuit and averaged to control the
VCO frequency.
1.2 Loop Filter
The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an
input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external
capacitor and resistor connected to the LPF pin and ground as shown below.
ZL30406
Internal Loop
Filter
LPF
RF
CF
RF=8.2 kΩ, CF=470 nF
(for 14 kHz PLL bandwidth)
Figure 3 - External Loop Filter
1.3 VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the
voltage of the error signal, generates a primary frequency. The VCO output is connected to the Output Interface
Circuit that divides VCO frequency and buffers generated clocks.
5
Zarlink Semiconductor Inc.
5 Page 
ZL30406
Data Sheet
2.3 Tristating LVPECL Outputs
The ZL30406 has four differential 77.76 MHz LVPECL outputs, which can be used to drive four different OC-3/OC-
12/OC-48 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required,
a user can disable unused LVPECL outputs on the ZL30406 by pulling the corresponding enable pins low. When
disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V.
For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling capacitors can be
used as shown in Figure 10. Typically this might be required in hot swappable applications.
Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC
coupling capacitors. During disable mode (C77oEN pin pulled low) those capacitors present infinite impedance to
the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6
are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the
LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4,
R5 and R6 should not be populated.
C77oEN
ZL30406
C1
0.1 u
C2
R1 R2 0.1 u
200 200
Z=50
3.3 V 3.3 V
R3 R5
127 127
Z=50
R4 R6
82.5 82.5
Figure 10 - Tristatable LVPECL Outputs
11
Zarlink Semiconductor Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet ZL30406.PDF ] | |
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