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PS11013 반도체 회로 부품 판매점

FLAT-BASE TYPE INSULATED TYPE



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PS11013 데이터시트, 핀배열, 회로
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PS11PS01113013
FLAFTL-BATA-SBEASTEYPTEYPE
INSIUNLSAUTLEADTETDYPTEYPE
PS11013
INTEGRATED FUNCTIONS AND FEATURES
• Converter bridge for 3 phase AC-to-DC power conversion.
• Circuit for dynamic braking of motor regenerative energy.
• 3-phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technology.
• Inverter output current capability IO (Note 1):
Type Name
100% load
150% over load
PS11013
3.0A (rms)
4.5A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : IOP = IO × √2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC).
Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV).
• For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC).
Control supply circuit under- & over- voltage protection (OV/UV).
System over temperature protection (OT). Fault output signaling circuit (FO) and Current limit warn-
ing signal output (CL).
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling :
FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
FO2 : N-side control supply abnormality locking (OV/UV).
FO3 : System over-temperature protection (OT).
CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
APPLICATION
Acoustic noise-less 0.4kW/AC200V class 3 phase inverter and other motor control applica-
tions
PACKAGE OUTLINES
4-R2
0.5
12 3 4 5 6 7 8 91011121314151617181920212223
24
2424
2 ± 0.3
2
2-φ4
2-R4
4.14 5.08 ± 0.3 ! 9 = 45.72 ± 0.8
31 32 33 34 35 36 37 38 39 40
1.2
(Fig. 1)
LABEL
54 ± 0.5
62 ± 1
V6
V Control Pin top
portion details
0.3
0.5 ± 0.03
Terminals Assignment:
1 CBU+
2 CBU–
3 CBV+
4 CBV–
5 CBW+
6 CBW–
7 GND
8 NC
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
21 VN
22 WN
23 Br
31 R
32 S
33 T
34 P1
35 P2
36 N
37 B
38 U
39 V
40 W
V Main terminal top
portion details
0.8
±
0.5
0
0.35MAX
12
±
0.5
0
0.6
Jan. 2000


PS11013 데이터시트, 핀배열, 회로
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
INTERNAL FUNCTIONS BLOCK DIAGRAM
C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change
depending on the type PWM control scheme used in the applied system)
C4 ; 2µF R-category ceramic condenser for noise filtering.
Application Specific Intelligent
Power Module
Brake resistor
P2
connection,
B
Inrush prevention
circuit, etc.
P1
Protection
Circuit
Level shifter
Drive Circuit
AC200V line input
R
S
T
U
MV
W
ZC
N
T.S. AC 200V line
output
Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit maybe necessary
depending on the application environment].
Current sensing
circuit
Trig signal conditioning
Drive Curcuit
FO Logic Protection
circuit
Control supply
fault sense
CU CV CW
UPVPWPUN VNWN Br CL FO1 FO2 FO3
C2 ;
C2 3.3µF or more
Analogue signal output corresponding to Each phase input (PWM) Fault output
each phase current (5V line) Note 1)
(5V line) Note 2) (5V line) Note 3)
GND VDH
(15V line)
Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10)
Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10)
Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kresistance. (see also Fig.10)
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra
precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins.
(Fig. 2)
MAXIMUM RATINGS (Tj = 25°C)
INVERTER PART (Including Brake Part)
Symbol
VCC
VCC(surge)
VP or VN
VP(S) or VN(S)
±IC(±ICP)
IC(ICP)
IF(IFP)
Item
Supply voltage
Supply voltage (surge)
Each output IGBT collector-emitter static voltage
Each output IGBT collector-emitter
switching surge voltage
Each output IGBT collector current
Brake IGBT collector current
Brake diode anode current
Condition
Applied between P2-N
Applied between P2-N, Surge-value
Applied between P-U, V, W, Br or U, V, W,
Br-N
Applied between P-U, V, W, Br or U, V, W,
Br-N
TC = 25°C
Note: “( )” means IC peak value
CONVERTER PART
Symbol
VRRM
Ea
IO
IFSM
I2t
Item
Repetitive peak reverse voltage
Recommended AC input voltage
DC output current
Surge (non-repetitive) forward current
I2t for fusing
Condition
3φ rectifying circuit
1 cycle at 60Hz, peak value non-repetitive
Value for one cycle of surge current
CONTROL PART
Symbol
VDH, VDB Supply voltage
Item
VCIN
VFO
IFO
VCL
ICL
ICO
Input signal voltage
Fault output supply voltage
Fault output current
Current-limit warning (CL) output voltage
CL output current
Analogue current signal output current
Condition
Applied between VDH-GND, CBU+-CBU–,
CBV+-CBV–, CBW+-CBW–
Applied between UP · VP · WP · UN · VN ·
WN · Br-GND
Applied between FO1 · FO2 · FO3-GND
Sink current of FO1 · FO2 · FO3
Applied between CL-GND
Sink current of CL
Sink current of CU · CV · CW
Ratings
450
500
600
600
±8 (±16)
3 (6)
3 (6)
Ratings
800
220
25
138
80
Ratings
20
–0.5 ~ 7.5
–0.5 ~ 7
15
–0.5 ~ 7
15
±1
Unit
V
V
V
V
A
A
A
Unit
V
V
A
A
A2s
Unit
V
V
V
mA
V
mA
mA
Jan. 2000




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