|
|
PDF NM24W02 Data sheet ( Hoja de datos )
| Número de pieza | NM24W02 | |
| Descripción | 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect | |
| Fabricantes | Fairchild | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NM24W02 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
PRELIMINARY
March 1999
NM24Wxx
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
General Description
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-
tively, of CMOS non-volatile electrically erasable memory. These
devices conform to all specifications in the IIC 2-wire protocol and
are designed to minimize device pin count, and simplify PC board
layout requirements.
The entire ememory can be disabled (Write Protected) by con-
necting the WP pin to VCC. The memory then becomes unalterable
unless WP is switched to VSS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by Fairchild's family in 2K,
4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consump-
tion.
Features
s Hardware Write Protect for entire memory
s Low Power CMOS
200µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
s IIC Compatible interface
— Provides bidirectional data transfer protocol
s Sixteen byte page write mode
— Minimizes total write time per byte
s Self timed write cycle
— Typical write cycle time of 6ms
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
s Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
VCC
VSS
WP
SDA
SCL
A2
A1
A0
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
XDEC
16/
32/
64/
128/
0/1/2/3
4
4
E2PROM
ARRAY
16
YDEC
Device Address Bits
DIN
8
CK
DATA REGISTER
DOUT
© 1999 Fairchild Semiconductor Corporation
NM24Wxx Rev. C.2
1
DS500074-1
www.fairchildsemi.com
1 page  
Bus Timing
tF
tHIGH
tLOW
SCL
SDA
tSU:STA
tHD:STA
,,IN
SDA
OUT
tAA
Background Information (IIC Bus)
tHD:DAT
As mentioned, the IIC bus allows synchronous bidirectional com-
munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condi-
tion.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROMs, etc., a devce type identifier string must
follow the START condition. For EEPROMs, this 4-bit string is
1010 and is the first 4 bits in the slave address.
As shown below, the EEPROMs on the IIC bus may be configured
in any manner required, and for the Standard IIC protocol, the total
memory addressed can not exceed 16K (16,384 bits). EEPROM
memory address programming is controlled by 2 methods:
• Hardware configuring the A0, A1, and A2 pins (Device
Address pins) with pull-up or pull-down to resistors. All
unused pins must be grounded (tied to VSS).
• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Addressing an EEPROM memory location involves sending a
command string with the following information:
tR
tLOW
tSU:DAT
tSU:STO
tDH
tBUF
DS500074-5
WORD
PAGE
PAGE BLOCK
MASTER
SLAVE
TRANSMITTER
RECEIVER
DEFINITIONS
8 bits of data
16 sequential addresses (one byte
each) that may be programmed
during a 'Page Write' programming
cycle
2,048 (2K) bits organized into 16
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) = 2,048
bits
Any IIC device CONTROLLING the
transfer of data (such as a micropro-
cessor)
Device being controlled (EEPROMs
are always considered Slaves)
Device currently SENDING data on
the bus (may be either a Master or
Slave).
Device currently receiving data on the
bus (Master or Slave)
[DEVICE TYPE]—[DEVICE ADDRESS]—[PAGE BLOCK
ADDRESS]—[BYTE ADDRESS]
Example of 16K of Memory on 2-Wire Bus
VCC
VCC
SDA
SCL
VCC
VCC
VCC
VCC
NM24W02
A0 A1 A2 VSS
NM24W02
A0 A1 A2 VSS
NM24W04
A0 A1 A2 VSS
NM24W08
A0 A1 A2 VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
To VCC or VSS
DS500074-6
NM24Wxx Rev. C.2
5 www.fairchildsemi.com
5 Page 
Read Operations (Continued)
Typical System Configuration (Figure 11)
VCC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
Note: Due to open drain configuration of SDA, a bus-level resistor is called for (Typical value = 4.7Ω)
DS500074-17
NM24Wxx Rev. C.2
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet NM24W02.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NM24W02 | 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect | Fairchild |
| NM24W04 | 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect | Fairchild |
| NM24W08 | 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect | Fairchild |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |