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PDF NJ88C22 Data sheet ( Hoja de datos )
| Número de pieza | NJ88C22 | |
| Descripción | Frequency Synthesiser with resettable counters | |
| Fabricantes | Zarlink Inc | |
| Logotipo |  |
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NJ88C22
Frequency Synthesiser with resettable counters
DS2439 - 2.2
The NJ88C22 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable ‘M’ counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although 28 bits of data are initially
required to program all counters, subsequent updating can be
abbreviated to 17 bits, when only the ‘A’ and ‘M’ counters require
changing.
The NJ88C22 is intended to be used in conjunction with a
two-modulus prescaler such as the SP8715 series to produce a
universal binary coded synthesiser for up to 1100MHz operation.
FEATURES
s Low Power Consumption
s High Performance Sample and Hold Phase Detector
s Serial Input with Fast Update Feature
s >20MHz Input Frequency
s Fast Lock-up Time
ORDERING INFORMATION
NJ88C22 MA DG Ceramic DIL Package
NJ88C22 MA DP Plastic DIL Package
NJ88C22 MA MP Miniature Plastic DIL Package
PDA 1
16 CH
PDB 2
15 RB
LD
FIN
VSS
VDD
OSC IN
OSC OUT
3 14
4 13
NJ88C22
5 12
6 11
7 10
89
DG16, DP16
MC
PDA
CAP
PDB
ENABLE
NC
LD
CLOCK
FIN
DATA
VSS
VDD
NC
NC OSC IN
1 18
2 17
3 16
4 15
5 NJ88C22 14
6 13
7 12
8 11
9 10
MP18
CH
RB
MC
CAP
ENABLE
CLOCK
DATA
NC
OSC OUT
Fig.1 Pin connections - top view (not to scale)
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD2VSS:
Input voltage
20·75V to 7V
Open drain output, LD pin:
7V
All other pins:
Storage temperature:
VSS20·3V to VDD10·3V
255°C to 1125°C
(DP and MP packages)
265°C to 1150°C
(DG package)
7 (9)
OSC IN
8 (10)
OSC OUT
10 (12)
DATA 12 (14)
ENABLE
11 (13)
CLOCK
REFERENCE COUNTER
(11BITS)
LATCH 6 LATCH 7 LATCH 8
‘R’ REGISTER
‘M’ REGISTER
LATCH 1 LATCH 2 LATCH 3
÷42 fr
RB CAP CH
15 17 16
(17) (15) (18)
SAMPLE/HOLD 1 (1)
PHASE
PDA
DETECTOR
fV
‘A’ REGISTER
LATCH 4 LATCH 5
FREQUENCY/ 2 (2)
PHASE
PDB
DETECTOR
3 (4)
LOCK DETECT (LD)
VSS
4 (5)
FIN
6 (7)
VDD
5 (6)
VSS
‘M’ COUNTER
(10 BITS)
‘A’ COUNTER
(7 BITS)
CONTROL LOGIC
Fig.2 Block diagram (MP pinout shown in parentheses)
14 (16) MODULUS
CONTROL
OUTPUT (MC)
1 page  
NJ88C22
12345
CLOCK
ENABLE
DATA
A6
A5
A4 A3
A2
(15)26 (16)27 (17)28
(M2)R2 (M1)R1 (M0)R0
Fig.6 Timing diagram showing programming details
PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain:
KPD KVCO
N
where KPD is the phase detector constant (volts/rad), KVCO is
the VCO constant (rad/sec/volt) and N is the overall loop division
ratio. When N is large and the loop gain is low, noise may be
reduced by employing a phase comparator with a high gain.
The sample and hold phase comparator in the NJ88C22 has
a high gain and uses a double sampling technique to reduce
spurious outputs to a low level.
A standard digital phase/frequency detector driving a three-
state output,PDB, provides a ‘coarse’ error signal to enable
fast switching between channels.
The PDB output is active until the phase error is within the
sample and hold phase detector window, when PDB becomes
high impedance. Phase-lock is indicated at this point by a low
level on LD. The sample and hold phase detector provides a
‘fine’ error signal to give further phase adjustment and to hold
the loop in lock. An internally generated ramp, controlled by the
digital output from both the reference and main divider chains,
is sampled at the reference frequency to give the ‘fine’ error
signal, PDA. When in phase lock, this output would be typically
at (VDD2VSS)/2 and any offset from this would be proportional
to phase error.
The relationship between this offset and the phase error is
the phase comparator gain, KPDA, which is programmable with
an external resistor, RB, and a capacitor, CAP. An internal
50pF capacitor is used in the sample and hold comparator.
CRYSTAL OSCILLATOR
When using the internal oscillator, the stability may be
enhanced at high frequencies by the inclusion of a resistor
between the OSC OUT pin and the other components. A value
of between 150Ω and 270Ω is advised, depending on the
crystal series resistance.
PROGRAMMING/POWER UP
Data and signal input pins should not have input applied to
them prior to the application of VDD, as otherwise latch-up may
occur.
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet NJ88C22.PDF ] | |
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