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PDF ML2003 Data sheet ( Hoja de datos )
| Número de pieza | ML2003 | |
| Descripción | Logarithmic Gain/Attenuator | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML2003 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
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ML2003, ML2004
Logarithmic Gain/Attenuator
www.fairchildsemi.com
Features
• Low noise: 0 dBrnc max with +24dB gain
• Low harmonic distortion: -60dB max
• Gain range: –24 to +24dB
• Resolution: 0.1dB steps
• Flat frequency response:
±0.05dB from .3–4 kHz
±0.10dB from .1-20 kHz
• Low supply current 4mA max from ±5V supplies
• TTL/CMOS compatible digital interface
• ML2003 has pin selectable serial or parallel interface;
ML2004 serial interface only
General Description
The ML2003 and ML2004 are digitally controlled logarith-
mic gain/attenuators with a range of –24 to +24 dB in 0.1 dB
steps.
The gain settings are selected by a 9-bit digital word.
The ML2003 digital interface is either parallel or serial.
The ML2004 is packaged in a 14-pin DIP with a serial
interface only.
Absolute gain accuracy is 0.05dB max over supply tolerance
of ±10% and temperature range.
These CMOS logarithmic gain/attenuators are designed for a
wide variety of applications in telecom, audio, sonar, or gen-
eral purpose function generation. One specific intended
application is analog telephone lines.
Block Diagram
VCC
PDN A GND VSS GND
Pin Connections
ML2003
18-PIN DIP
VIN +
COURSE
–
RESISTORS/
SWITCHES
16
+
FINE
–
RESISTORS/
SWITCHES
16
+
BUFFER
–
DECODER/MODE SELECTOR
C2
(LATI)
C1
(SID)
C0
C1
C2
F0
F2
9
9-BIT LATCH &
SHIFT REGISTER
ATTEN/
GAIN
C3 F1 F3
F2
(SCK)
NOTE: SERIAL MODE FUNCTIONS INDICATED BY PARENTHESES.
VOUT
C3
(LATI)C2
(SID)C1
(LATO)C0
PDN
F3
(SCK)F2
F1
GND
SER/PAR
C0
(LATO)
F0
(SOD)
LATI
SID
LATO
PDN
SCK
NC
GND
1 18
2 17
3 16
4 15
5 14
6 13
7 12
8 11
9 10
TOP VIEW
ML2004
14-PIN DIP
1 14
2 13
3 12
4 11
5 10
69
78
ATTEN/GAIN
VCC
VOUT
VSS
A GND
VIN
NC
F0 (SOD)
SER/PAR
C0 (LATO)
NC
PDN
F3
F2 (SCK)
VCC
VOUT
VSS
A GND
VIN
NC
SOD
ML2003
20-Pin PCC
3 2 1 20 19
4 18
5 17
6 16
7 15
8 14
9 10 11 12 13
TOP VIEW
VOUT
VSS
A GND
NC
NC
TOP VIEW
REV. 1.1.1 3/19/01
1 page  
PRODUCT SPECIFICATION
Timing Diagram
SCK
SID
SOD
SCK
LATI
LATO
SOD
tS
tD
tSCK
tSCK
tH
tIS tIH
tIPW
tOS tOH
tOPW
tPLD
TIMING PARAMETERS ARE REFERENCED TO THE 1.4 VOLT MIDPOINT.
Figure 1. Serial Mode Timing Diagram
ML2003, ML2004
Typical Performance Curves
0
-0.5
-0.10
-0.15
-0.20
-0.25
-0.30
ATTEN: VIN = 0.5VRMS
GAIN: VIN = 0.5VRMS/GAIN SETTING
GAIN = +24dB
GAIN = +18dB
GAIN = +12dB
GAIN = +0, -24dB
-0.35
-0.40
-0.45
-0.50
100
1K 10K
FREQUENCY (Hz)
100K
Figure 2. Amplitude vs Frequency (VIN/VOUT = .5VRMS)
0
-0.5
-0.10
-0.15
-0.20
-0.25
ATTEN: VIN = 2VRMS
GAIN: VIN = 2VRMS/GAIN SETTING
GAIN = +24dB
GAIN = 0dB
GAIN = –24dB
-0.30
-0.35
-0.40
-0.45
-0.50
100
1K 10K
FREQUENCY (Hz)
100K
Figure 3. Amplitude vs Frequency (VIN/VOUT = 2VRMS)
REV. 1.1.1 3/19/01
5
5 Page 
ML2003, ML2004
Ordering Information
Part Number
ML2003IQ
ML2003CP
ML2003CQ
ML2004IP
ML2004CP
Temperature Range
-40°C to 85°C
0°C to 70°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
PRODUCT SPECIFICATION
Package
Molded PCC (Q20)
Molded DIP (P18)
Molded PCC (Q20)
Molded DIP (P14)
Molded DIP (P14)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
3/19/01 0.0m 003
Stock#DS300042003
2001 Fairchild Semiconductor Corporation
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ML2003.PDF ] | |
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