파트넘버.co.kr MK2042-01 데이터시트 PDF


MK2042-01 반도체 회로 부품 판매점

Communications Clock Monitor



Integrated Circuit Systems 로고
Integrated Circuit Systems
MK2042-01 데이터시트, 핀배열, 회로
I
C
R
O
ADVANCE
C LOC K
INFORMATION
Communications
MK2042-01
Clock Monitor
Description
The MK2042-01 is designed to switch between
two clock sources. The switching can be externally
controlled by an input pin or configured to switch
automatically if the primary input clock stops.
The part also provides clock detection by reporting
when the primary input clock has stopped.
The MK2042-01 is optimized for use with our
MK2049 family of Communication Clock
Synthesizers. When used together, the
MK2042-01 and MK2049 provide a complete
system for switching to an alternate source when
the primary clock is lost, or for maintaining a
stable frequency on the MK2049 output.
For switching between clock sources with no
output glitches or short pulses, use the ICS580 or
ICS581 multiplexers.
Features
• Packaged in 16 pin SOIC
• User controlled or automatic switching
• Clock detect feature
• Does not add jitter or phase noise to the clock
• Ideal for systems with backup or redundant clocks
• Selectable timeouts for clock loss detection
• Accepts input frequencies from 0 Hz to 160 MHz
• Works with all MK2049-xx to provide enhanced
operation
• 3.3 V or 5 V operation
Block Diagram
VDD GND
SELB
OE
INB
INA
REFIN
S2:S0
CENTER
3
Clock Loss
Detector
VDD
CLKOUT
NO_INA
HIGH
GND
LOW
MDS 2042-01
1
Revision 102600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com


MK2042-01 데이터시트, 핀배열, 회로
I
C
R
O
ADVANCE
C LOC K
INFORMATION
Communications
MK2042-01
Clock Monitor
Pin Assignment
S0
S1
S2
INB
INA
GND
SELB
REFIN
1
2
3
4
5
6
7
8
16 OE
15 VDD
14 CLKOUT
13 NO_INA
12 HIGH
11 LOW
10 GND
9 CENTER
16 pin (150 mil) SOIC
Clock Loss Detector Settings
S2 S1 S0 Nominal Count
000
34
001
18
010
130
011
66
100
10
101
6
110
2
111
2
Due to the possible phase differences between
the REFIN clock and the INA clock, the
Nominal Count has a tolerance of -0/+1
REFIN clock edges.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
S0
S1
S2
INB
INA
GND
SELB
REFIN
CENTER
GND
LOW
HIGH
NO_INA
CLKOUT
VDD
OE
Type Description
I Clock Count Select 0. Determines allowed number of missing clock edges per table above.
I Clock Count Select 1. Determines allowed number of missing clock edges per table above.
I Clock Count Select 2. Determines allowed number of missing clock edges per table above.
I Input Clock B.
I Input Clock A.
P Connect to ground.
I Mux select. Selects INB when high.
I Reference Clock Input.
I Enables HIGH and LOW pins when high.
P Connect to ground.
O Sets low end of centering range.
O Sets high end of centering range.
O Goes high when clock on INA stops.
O Clock output.
P Connect to +3.3 V or +5 V.
I Output Enable. Tri-states CLKOUT when low.
Type: I = Input, O = output, P = power supply connection
All inputs have an internal pull-up.
MDS 2042-01
2
Revision 102600
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com




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