파트넘버.co.kr MK1574-01SITR 데이터시트 PDF


MK1574-01SITR 반도체 회로 부품 판매점

Frame Rate Communications PLL



Integrated Circuit Systems 로고
Integrated Circuit Systems
MK1574-01SITR 데이터시트, 핀배열, 회로
I CR O C LOC K
MK1574
Frame Rate Communications PLL
Description
The MK1574-01 is a Phase-Locked Loop (PLL)
based clock synthesizer, which accepts an 8 kHz
clock input as a reference, and generates many
popular communications frequencies. All outputs
are frequency locked together and to the input.
This allows for the generation of locked clocks to
the 8 kHz backplane clock, simplifying clock
generation and distribution in communications
systems.
MicroClock can customize this device for any
other different frequencies.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• Exact multiplications stored in the device eliminate
the need for external dividers
• Accepts 8 kHz input clock
• Output clock rates include T1, E1, T2, E2
• 3.0V to 5.5V operation
• Available in commercial (0 to +70 C) or industrial
(-40 to +85 C) temperature ranges
• For jitter attenuation, use the MK2049
Block Diagram
VDD GND
22
FS0-3
4
8kHz
Input Clock
Input
Buffer
PLL
Clock
Synthesis
and
Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
CAP1
CAP2
CLK1
CLK2
CLK3
8kHz
(recovered)
MDS 1574-01 D
1
Revision 011999
Printed 11/15/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax


MK1574-01SITR 데이터시트, 핀배열, 회로
I CR O C LOC K
MK1574
Frame Rate Communications PLL
Pin Assignment
Output Clocks Decoding Table MK1574-01 (MHz)
ICLK 1
16 FS3
Decode Address
FS3:0 (Hex)
VDD 2
15 N/C
0000 0
0001 1
VDD 3
14 FS2
0010 2
0011 3
CAP1 4
GND 5
13 FS1
12 CLK3
0100
0101
0110
4
5
6
CAP2 6
11 CLK2
0111 7
1000 8
GND 7
10 CLK1
1001 9
1010 A
FS0 8
9
8KOUT 1011
1100
B
C
16 pin (150 mil) SOIC
1101 D
1110 E
1111 F
ICLK
pin 1
Reserved
Reserved
Reserved
Reserved
8.00kHz
8.00kHz
8.00kHz
8.00kHz
8.00kHz
8.00kHz
8.00kHz
8.00kHz
8.00kHz
8.00kHz
8.00kHz
8.00kHz
Multiplier
On-chip
Reserved
Reserved
Reserved
Reserved
2940
1960
2760
2640
1920
6480
2112
1578
8192
6176
1024
772
CLK 1
pin 10
Reserved
Reserved
Reserved
Reserved
23.52
15.68
22.08
21.12
15.36
51.84
16.896
12.624
65.536
49.408
8.192
6.176
CLK 2
pin 11
Reserved
Reserved
Reserved
Reserved
11.76
7.84
11.04
10.56
7.68
25.92
8.448
6.312
32.768
24.704
4.096
3.088
• 0 = connect directly to ground, 1 = connect directly to VDD.
CLK 3
pin 12
Reserved
Reserved
Reserved
Reserved
5.88
3.92
5.52
5.28
3.84
12.96
4.224
3.156
16.384
12.352
2.048
1.544
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
ICLK
VDD
VDD
CAP1
GND
CAP2
GND
FS0
8KOUT
CLK1
CLK2
CLK3
FS1
FS2
N/C
FS3
Type Description
I Input clock. Connect to an 8kHz clock input.
P Connect to +3.3V or +5V.
P Connect to +3.3V or +5V. Must be same voltage as pin 2.
I Connect a ceramic capacitor and a resistor in series between this pin and CAP2. Refer to page 4.
P Connect to ground.
I Connect a ceramic capacitor and a resistor in series between this pin and CAP1. Refer to page 4.
P Connect to ground.
I Frequency Select 0. Determines CLK outputs per table above.
O Recovered 8kHz output clock. Can be lower jitter, better duty cycle than input clock.
O Clock 1 determined by status of FS3:0 per table above.
O Clock 2 determined by status of FS3:0 per table above.
O Clock 3 determined by status of FS3:0 per table above.
I Frequency Select 1. Determines CLK outputs per table above.
I Frequency Select 2. Determines CLK outputs per table above.
- No Connect. Nothing is connected to this pin.
I Frequency Select 3. Determines CLK outputs per table above.
Type: I = Input, O = output, P = power supply connection
MDS 1574-01 D
2
Revision 011999
Printed 11/15/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax




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MK1574-01SITR

Frame Rate Communications PLL - Integrated Circuit Systems