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PDF MK1574-01S Data sheet ( Hoja de datos )
| Número de pieza | MK1574-01S | |
| Descripción | Frame Rate Communications PLL | |
| Fabricantes | Integrated Circuit Systems | |
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I CR O C LOC K
MK1574
Frame Rate Communications PLL
Description
The MK1574-01 is a Phase-Locked Loop (PLL)
based clock synthesizer, which accepts an 8 kHz
clock input as a reference, and generates many
popular communications frequencies. All outputs
are frequency locked together and to the input.
This allows for the generation of locked clocks to
the 8 kHz backplane clock, simplifying clock
generation and distribution in communications
systems.
MicroClock can customize this device for any
other different frequencies.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• Exact multiplications stored in the device eliminate
the need for external dividers
• Accepts 8 kHz input clock
• Output clock rates include T1, E1, T2, E2
• 3.0V to 5.5V operation
• Available in commercial (0 to +70 C) or industrial
(-40 to +85 C) temperature ranges
• For jitter attenuation, use the MK2049
Block Diagram
VDD GND
22
FS0-3
4
8kHz
Input Clock
Input
Buffer
PLL
Clock
Synthesis
and
Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
CAP1
CAP2
CLK1
CLK2
CLK3
8kHz
(recovered)
MDS 1574-01 D
1
Revision 011999
Printed 11/15/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
1 page  
I CR O C LOC K
MK1574
Frame Rate Communications PLL
Loop Filter Constants
This table shows the constants K1 and K2 that are used with the equations on page 4 to calculate the
external loop filter components.
Loop Filter Constants for MK1574-01
Decode Address Loop Filter Constants
FS3:0 (Hex) K1
K2
0000 0 Reserved Reserved
0001 1 Reserved Reserved
0010 2 Reserved Reserved
0011 3 Reserved Reserved
0100 4
0.0430
7.4
0101 5
0.0527
6.0
0110 6
0.0444
7.2
0111 7
0.0454
7.0
1000 8
0.0533
6.0
1001 9
0.0410
7.8
1010 A 0.0508
6.3
1011 B 0.0587
5.4
1100 C
0.0365
8.7
1101 D 0.0420
7.6
1110 E
0.0516
6.2
1111 F
0.0594
5.4
PC Board Layout
A proper board layout is critical to the successful
use of the MK1574. In particular, the CAP1 and
CAP2 pins are very sensitive to noise and leakage
(CAP1 at pin 4 is the most sensitive). Traces
must be as short as possible and the capacitor
and resistor must be mounted next to the device
as shown to the right. The capacitor connected
between pins 3 and 5 is the power supply
decoupling capacitor.
The high frequency output clocks on may
benefit from a series 33Ω resistor connected
close to the pin (not shown).
1 16
V 2 15
3 14 V =connect to VDD
cap 4 13 G =connect to GND
cap G
resist.
5 12
6 11
7 10
89
Clock Multipliers/Accuracies
In the table on page 2 are the actual multipliers stored in the MK1574 ROM, which yield the exact values
shown for the output clocks.
MDS 1574-01 D
5
Revision 011999
Printed 11/15/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MK1574-01S.PDF ] | |
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