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MK1573-02STR 반도체 회로 부품 판매점

GenClock HSYNC to Video Clock



Integrated Circuit Systems 로고
Integrated Circuit Systems
MK1573-02STR 데이터시트, 핀배열, 회로
MK1573-02
GenClockHSYNC to Video Clock
Description
The MK1573 GenClock™ provides genlock
timing for video overlay systems. The device
accepts the horizontal sync (HSYNC) signal as the
input reference clock, and generates a frequency-
locked high speed output. Stored in the device are
the multipliers for 16 combinations of popular
frequencies for analog and digital TV and set-top
box systems. Frequency-locked outputs include
1X, 4X, and 8X the subcarrier frequencies of
NTSC and PAL systems, and 27MHz plus
13.5MHz for digital video systems. In most
selections, the chip recovers the HSYNC clock by
outputting a low jitter 50% duty cycle version of
HSYNC. Also available is an inverted recovered
HSYNC clock, and a double speed recovered
HSYNC clock.
MicroClock can customize this device for any
other different frequencies.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• The -02 version has one frequency changed
(32MHz was added), and tracks the HSYNC
better than the -01 version.
• Exact ratios stored in the device eliminate the need
for external dividers
• Accepts HSYNC of 15.625kHz or 15.73426kHz
• Highly accurate frequency generation within 1 ppm
• Generates NTSC/PAL subcarrier frequencies, and
4X and 8X of those frequencies
• Generates 27MHz and 13.5MHz
• 2X HSYNC clock available
• Recovered HSYNC clock available
• Inverted HSYNC clock available
• 4.5V to 5.5V operation
Block Diagram
FS0-3 4
HSYNC
Input Clock
VDD GND
22
Input
Buffer
Clock
Synthesis
and
Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
CLK3
OE (all outputs)
MDS 1573-02 B
1
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com


MK1573-02STR 데이터시트, 핀배열, 회로
MK1573-02
GenClockHSYNC to Video Clock
Pin Assignment
Output Clocks Decoding Table MK1573-02 (MHz)
HSYNC
VDD
VDD
CAP1
GND
CAP2
GND
FS0
1
2
3
4
5
6
7
8
16 FS3
15 N/C
14 FS2
13 FS1
12 CLK2
11 OE
10 CLK1
9 CLK3
16 pin (150 mil) SOIC
Pin Descriptions
Decode Address HSYNC Multiplier CLK 1
CLK 2
CLK 3
FS3:0 (Hex) pin 1 On-chip pin 10
pin 12
pin 9
0000 0 15.625k 1536
24M
12M 15.625k
0001 1 15.734264k 1525 1/3 24M
12M 15.734264k
0010 2 15.625k 1728 27M 13.5M 15.625k
0011 3 15.734264k 1716 27M 13.5M 15.734264k
0100 4
15.625k
960
15M
7.5M
15.625k
0101 5 15.734264k 953 1/3 15M
7.5M 15.734264k
0110 6 15.625k 3840
60M
30M 15.625k
0111 7 15.734264k 3840 60.41957M 30.20979M 15.734264k
1000 8 15.625k 2270 35.46875M 17.734375M 4.433594M
1001 9 15.734264k 1820 28.63636M 14.31818M 3.579545M
1010 A 15.625k 2270 35.46875M 15.625k 15.625k
1011 B 15.734264k 1820 28.63636M 15.734264k 15.734264k
1100 C 15.625k 2048
32M
16M 15.625k
1101 D 15.734264k 808 12.71329M 15.734264k 31.4685k
1110 E 15.625k 2270 35.46875M 15.625k 31.25k
1111 F 15.734264k 1820 28.63636M 15.734264k 31.4685k
• 0 = connect directly to ground, 1 = connect directly to VDD.
• CLK2 is a recovered HSYNC (with 50% duty cycle) on selections in italic.
• HSYNC reference outputs on CLK3 (in italic) are inverted, recovered HSYNC.
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
HSYNC
VDD
VDD
CAP1
GND
CAP2
GND
FS0
CLK3
CLK1
OE
CLK2
FS1
FS2
N/C
FS3
Type Description
I HSYNC clock input. The output clocks are synchronized to the HSYNC falling edge.
P Connect to +5V.
P Connect to +5V.
I Connect a 0.01µF ceramic capacitor and a 39kresistor in series between this pin and CAP2.
P Connect to ground.
I Connect a 0.01µF ceramic capacitor and a 39kresistor in series between this pin and CAP1.
P Connect to ground.
I Frequency Select 0. Determines CLK outputs (with given input) per table above.
O Clock 3 determined by status of FS3:0 per table above.
O Clock 1 determined by status of FS3:0 per table above.
I Output Enable. Tri-states the three output clocks when low.
O Clock 2 determined by status of FS3:0 per table above.
I Frequency Select 1. Determines CLK outputs (with given input) per table above.
I Frequency Select 2. Determines CLK outputs (with given input) per table above.
- No Connect. Nothing is connected to this pin.
I Frequency Select 3. Determines CLK outputs (with given input) per table above.
Type: I = Input, O = output, P = power supply connection
MDS 1573-02 B
2
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com




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GenClock HSYNC to Video Clock - Integrated Circuit Systems