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7C187-35 반도체 회로 부품 판매점

64K x 1 Static RAM



Cypress Semiconductor 로고
Cypress Semiconductor
7C187-35 데이터시트, 핀배열, 회로
87
CY7C187
Features
• High speed
— 15 ns
• CMOS for optimum speed/power
• Low active power
— 495 mW
• Low standby power
— 220 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C187 is a high-performance CMOS static RAM orga-
nized as 65,536 words x 1 bit. Easy memory expansion is pro-
64K x 1 Static RAM
vided by an active LOW Chip Enable (CE) and three-state driv-
ers. The CY7C187 has an automatic power-down feature,
reducing the power consumption by 56% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory location specified on
the address pins (A0 through A15).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied on the address pin will appear on the data output (DOUT)
pin.
The output pin stays in high-impedance state when Chip En-
able (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C187 utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
INPUT BUFFER
A12
A13
A14
A15 256 x 256
A0 ARRAY
A1
A2
A3
COLUMN DECODER
POWER
DOWN
Selection Guide[1]
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Note:
1. For military specifications, see the CY7C187A datasheet.
DI
DO
CE
SOJ
Top View
A0
A1
A2
A3
A4
A5
NC
A6
A7
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 A15
22 A14
21 A13
20 A12
19 NC
18 A11
17 A10
16 A9
15 A8
14 DIN
13 CE
C1873
WE
C1871
DIP
Top View
A0
A1
A2
A3
A4
A5
A6
A7
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
22 VCC
21 A15
20 A14
19 A13
18 A12
17 A11
16 A10
15 A9
14 A8
13 DIN
12 CE
C1872
7C187-15
15
90
40/20
7C187-20
20
80
40/20
7C187-25
25
70
20/20
7C187-35
35
70
20/20
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05044 Rev. **
Revised August 24, 2001


7C187-35 데이터시트, 핀배열, 회로
CY7C187
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65°C to +150°C
Ambient Temperature with
Power Applied............................................. 55°C to +125°C
Supply Voltage to Ground Potential
(Pin 22 to Pin 11) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[2] ............................................ 0.5V to +7.0V
DC Input Voltage[2] .........................................0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MILSTD883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
VCC
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage[2]
IIX Input Load Current
IOZ Output Leakage
Current
IOS
Output Short
Circuit Current[3]
ICC VCC Operating
Supply Current
ISB1
Automatic CE Power-
Down Current[4]
ISB2 Automatic CE
Power-Down Current
Test Conditions
VCC = Min.,
IOH = 4.0 mA
VCC = Min.,
IOL=12.0 mA
GND < VI < VCC
GND < VO < VCC,
Output Disabled
VCC = Max.,
VOUT = GND
VCC = Max.,
IOUT = 0 mA
Max. VCC, CE VIH
Max. VCC,
CE VCC 0.3V,
VIN VCC 0.3V
or VIN 0.3V
7C187-15
Min. Max.
2.4
7C187-20
Min. Max.
2.4
7C187-25, 35
Min. Max.
2.4
Unit
V
0.4 0.4
0.4 V
2.2 VCC 2.2 VCC
0.5 0.8 0.5 0.8
2.2
0.5
VCC
0.8
V
V
5 +5 5 +5
5
+5 µA
5 +5 5 +5
5
+5 µA
350
350
350 mA
90 80
70 mA
40 40
20 mA
20 20
20 mA
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
CIN
COUT
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
10 pF
10 pF
Notes:
2. VIL (min.) = 3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05044 Rev. **
Page 2 of 9




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7C187-35

64K x 1 Static RAM - Cypress Semiconductor