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PDF M80C186 Data sheet ( Hoja de datos )
| Número de pieza | M80C186 | |
| Descripción | CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR | |
| Fabricantes | Intel | |
| Logotipo |  |
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M80C186
CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR
Military
Y Operation Modes Include
Enhanced Mode Which Has
DRAM Refresh
Power-Save Logic
Direct Interface to New CMOS
Numerics Coprocessor
Compatible Mode
NMOS M80186 Pin-for-Pin
Replacement for Non-Numerics
Applications
Y Integrated Feature Set
Enhanced M80C86 C88 CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
Power Save Logic
System-Level Testing Support (High
Impedance Test Mode)
Y Available in 10 MHz and 12 5 MHz
Versions
Y Direct Addressing Capability to
1 Mbyte and 64 Kbyte I O
Y Completely Object Code Compatible
with All Existing M8086 M8088
Software and Also Has 10 Additional
Instructions over M8086 M8088
Y Complete System Development
Support
All M8086 and NMOS M80186
Software Development Tools Can Be
Used for M80C186 System
Development
Assembler PL M Pascal Fortran
and System Utilities
In-Circuit-Emulator (ICETM-C186)
Y Available in 68-Pin Ceramic Pin Grid
Array (PGA) and 68-Lead Ceramic Quad
Flat Pack
(See Packaging Outlines and Dimensions Order 231369)
Y Available in Two Product Grades
MIL-STD-883 b55 C to a125 C (TC)
Military Temperature Only (MTO)
b55 C to a125 C (TC)
The Intel M80C186 is a CHMOS high integration microprocessor It has features which are new to the M80186
family which include a DRAM refresh control unit power-save mode and a direct numerics interface When
used in ‘‘compatible’’ mode the M80C186 is 100% pin-for-pin compatible with the NMOS M80186 (except for
M8087 applications) The ‘‘enhanced’’ mode of operation allows the full feature set of the M80C186 to be
used The M80C186 is upward compatible with M8086 and M8088 software and fully compatible with M80186
and M80188 software
November 1993
Figure 1 M80C186 Block Diagram
270500 – 1
Order Number 270500-008
1 page  
Symbol
BHE
ALE QS0
WR QS1
RD QSMD
M80C186
PGA
64
61
63
62
Table 1 M80C186 Pin Description (Continued)
QFP
14
17
15
16
Type
O
O
O
O
Name and Function
The BHE (Bus High Enable) signal is analogous to A0 in that
it is used to enable data on to the most significant half of the
data bus pins D15 – D8 BHE will be LOW during T1 when the
upper byte is transferred and will remain LOW through T3
AND TW BHE does not need to be latched BHE will float
during HOLD
In Enhanced Mode BHE will also be used to signify DRAM
refresh cycles A refresh cycle is indicated by BHE and A0
being HIGH
BHE and A0 Encodings
BHE Value
A0 Value
Function
0 0 Word Transfer
0 1 Byte Transfer on upper half
of data bus (D15 – D8)
1 0 Byte Transfer on lower half
of data bus (D7 – D0)
1 1 Refresh
Address Latch Enable Queue Status 0 is provided by the
M80C186 to latch the address ALE is active HIGH
Addresses are guaranteed to be valid on the trailing edge of
ALE The ALE rising edge is generated off the rising edge of
the CLKOUT immediately preceding T1 of the associated bus
cycle effectively one-half clock cycle earlier than in the
standard M8086 The trailing edge is generated off the
CLKOUT rising edge in T1 as in the M8086 Note that ALE is
never floated
Write Strobe Queue Status 1 indicates that the data on the
bus is to be written into a memory or an I O device WR is
active for T2 T3 and TW of any write cycle It is active LOW
and floats during ‘‘HOLD ’’ It is driven HIGH for one clock
during Reset and then floated When the M80C186 is in
queue status mode the ALE QS0 and WR QS1 pins provide
information about processor instruction queue interaction
QS1
QS0
Queue Operation
0 0 No queue operation
0 1 First opcode byte fetched
from the queue
1 1 Subsequent byte fetched
from the queue
1 0 Empty the queue
Read Strobe indicates that the M80C186 is performing a
memory or I O read cycle RD is active LOW for T2 T3 and
TW of any read cycle It is guaranteed not to go LOW in T2
until after the Address Bus is floated RD is active LOW and
floats during ‘‘HOLD’’ RD is driven HIGH for one clock
during Reset and then the output driver is floated A weak
internal pull-up mechanism of the RD line holds it HIGH when
the line is not driven During RESET the pin is sampled to
determine whether the M80C186 should provide ALE WR
and RD or if the Queue-Status should be provided RD
should be connected to GND to provide Queue-Status data
5
5 Page 
M80C186
Table 2 Status Word Bit Functions
Bit
Position
Name
Function
0 CF Carry Flag Set on high-order
bit carry or borrow cleared
otherwise
2 PF Parity Flag Set if low-order 8
bits of result contain an even
number of 1-bits cleared
otherwise
4 AF Set on carry from or borrow to
the low order four bits of AL
cleared otherwise
6 ZF Zero Flag Set if result is zero
cleared otherwise
7 SF Sign Flag Set equal to high-
order bit of result (0 if positive
1 if negative)
8 TF Single Step Flag Once set a
single step interrupt occurs
after the next instruction
executes TF is cleared by the
single step interrupt
9 IF Interrupt-enable Flag When
set maskable interrupts will
cause the CPU to transfer
control to an interrupt vector
specified location
10 DF Direction Flag Causes string
instructions to auto decrement
the appropriate index register
when set Clearing DF causes
auto increment
11 OF Overflow Flag Set if the
signed result cannot be
expressed within the number
of bits in the destination
operand cleared otherwise
Instruction Set
The instruction set is divided into seven categories
data transfer arithmetic shift rotate logical string
manipulation control transfer high-level instruc-
tions and processor control These categories are
summarized in Figure 4
An M80C186 instruction can reference anywhere
from zero to several operands An operand can re-
side in a register in the instruction itself or in memo-
ry Specific operand addressing modes are dis-
cussed later in this data sheet
Memory Organization
Memory is organized in sets of segments Each seg-
ment is a linear contiguous sequence of up to 64K
(216) 8-bit bytes Memory is addressed using a two-
component address (a pointer) that consists of a 16-
bit base segment and a 16-bit offset The 16-bit
base values are contained in one of four internal
segment register (code data stack extra) The
physical address is calculated by shifting the base
value LEFT by four bits and adding the 16-bit offset
value to yield a 20-bit physical address (see Figure
5) This allows for a 1 MByte physical address size
All instructions that address operands in memory
must specify the base segment and the 16-bit offset
value For speed and compact instruction encoding
the segment register used for physical address gen-
eration is implied by the addressing mode used (see
Table 3) These rules follow the way programs are
written (see Figure 6) as independent modules that
require areas for code and data a stack and access
to external data areas
Special segment override instruction prefixes allow
the implicit segment register selection rules to be
overridden for special cases The stack data and
extra segments may coincide for simple programs
11
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