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M80287 반도체 회로 부품 판매점

80-BIT HMOS* NUMERIC PROCESSOR EXTENSION



Intel 로고
Intel
M80287 데이터시트, 핀배열, 회로
M80287
80-BIT HMOS
NUMERIC PROCESSOR EXTENSION
Military
Y High Performance 80-Bit Internal
Architecture
Y Implements Proposed IEEE Floating
Point Standard 754
Y Expands M80286 10 Datatypes to
Include 32- 64- 80-Bit Floating Point
32- 64-Bit Integers and 18-Digit BCD
Operands
Y Object Code Compatible with M8087
Y Built-In Exception Handling
Y Operates in Both Real and Protected
Mode M80286 Systems
Y Available in a 40-Pin Cerdip Package
Y Protected Mode Operation Completely
Conforms to the M80286 Memory
Management and Protection
Mechanisms
Y Directly Extends M80286 10 Instruction
Set to Trigonometric Logarithmic
Exponential and Arithmetic Instructions
for All Datatypes
Y 8 x 80-Bit Individually Addressable
Numeric Register Stack
Y 6 8 10 MHz
Y Military Temperature Range
b55 C to a125 C (TC)
The Intel M80287 is a high performance numerics processor extension that extends the M80286 10 architec-
ture with floating point extended integer and BCD data types The M80286 20 computing system (M80286
and M80287) fully conforms to the proposed IEEE Floating Point Standard Using a numerics oriented archi-
tecture the M80287 adds over fifty mnemonics to the M80286 20 instruction set making the M80286 20 a
complete solution for high performance numeric processing The M80287 is implemented in N-channel deple-
tion load silicon gate technology (HMOS) and packaged in a 40-pin ceramic package The M80286 20 is
object code compatible with the M80286 20 and M8088 20 Intel’s HMOS III process provides superior
radiation tolerance for applications with stringent radiation requirements
HMOS is a patented process of Intel Corporation
Figure 1 M80287 Block Diagram
271029 – 1
NOTE
271029 – 2
N C pins must not be connected
Figure 2 M80287 Pin
Configuration
December 1990
Order Number 271029-005


M80287 데이터시트, 핀배열, 회로
M80287
Symbol
CLK
CKM
RESET
D15 – D0
BUSY
ERROR
PEREQ
PEACK
NPRD
NPWR
NPS1 NPS2
CMD1 CMD0
CLK286
S1 S0
COD INTA
HLDA
READY
VSS
VCC
2
Type
I
I
I
IO
O
O
O
I
I
I
I
I
I
I
I
I
I
I
Table 1 M80287 Pin Description
Name and Function
CLOCK INPUT This clock provides the basic timing for internal M80287
operations Special MOS level inputs are required The M82284 or M8284A
CLK outputs are compatible to this input
CLOCK MODE SIGNAL Indicates whether CLK input is to be divided by 3
or used directly A HIGH input will select the latter option This input may be
connected to VCC or VSS as appropriate This input must be either HIGH or
LOW 20 CLK cycles before RESET goes LOW
SYSTEM RESET Causes the M80287 to immediately terminate its present
activity and enter a dormant state RESET is required to be HIGH for more
than 4 M80287 CLK cycles For proper initialization the HIGH-LOW
transition must occur no sooner than 50 ms after VCC and CLK meet their
D C and A C specifications
DATA 16-bit bidirectional data bus Inputs to these pins may be applied
asynchronous to the M80287 clock
BUSY STATUS Asserted by the M80287 to indicate that it is currently
executing a command
ERROR STATUS Reflects the ES bit of the status word This signal
indicates that an unmasked error condition exists
PROCESSOR EXTENSION DATA CHANNEL OPERAND TRANSFER
REQUEST A HIGH on this output indicates that the M80287 is ready to
transfer data PEREQ will be disabled upon assertion of PEACK or upon
actual data transfer whichever occurs first if no more transfers are required
PROCESSOR EXTENSION DATA CHANNEL OPERAND TRANSFER
ACKNOWLEDGE Acknowledges that the request signal (PEREQ) has been
recognized Will cause the request (PEREQ) to be withdrawn in case there
are no more transfers required PEACK may be asynchronous to the
M80287 clock
NUMERIC PROCESSOR READ Enables transfer of data from the M80287
This input may be asynchronous to the M80287 clock
NUMERIC PROCESSOR WRITE Enables transfer of data to the M80287
This input may be asynchronous to the M80287 clock
NUMERIC PROCESSOR SELECTS Indicates the CPU is performing an
ESCAPE instruction Concurrent assertion of these signals (i e NPS1 is
LOW and NPS2 is HIGH) enables the M80287 to perform floating point
instructions No data transfers involving the M80287 will occur unless the
device is selected via these lines These inputs may be asynchronous to the
M80287 clock
COMMAND LINES These along with select inputs allow the CPU to direct
the operation of the M80287 No actions will occur if these signals are both
HIGH These inputs may be asynchronous to the M80287 clock
CPU CLOCK This input provides a sampling edge for the M80287 inputs
S1 S0 COD INTA READY and HLDA It must be connected to the
M80286 CLK input
STATUS These inputs allow the M80287 to monitor the execution of
ESCAPE instructions by the M80286 They must be connected to the
corresponding M80286 pins
HOLD ACKNOWLEDGE This input informs the M80287 when the M80286
controls the local bus It must be connected to the M80286 HLDA output
READY The end of a bus cycle is signaled by this input It must be
connected to the M80286 READY input
GROUND System ground both pins must be connected to ground
POWER a5V supply




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80-BIT HMOS* NUMERIC PROCESSOR EXTENSION - Intel