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PDF 74VHCT574A Data sheet ( Hoja de datos )
| Número de pieza | 74VHCT574A | |
| Descripción | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74VHCT574A
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE VOLP = 0.9V (Max.)
DESCRIPTION
The 74VHCT574A is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP with 3
STATE OUTPUT NON INVERTING fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHCT574AM
74VHCT574AT
outputs will be set to logic states that were setup
at the D inputs.
While the OE input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and,
while high level, the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 1999
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1 page  
74VHCT574A
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
Value
Un it
TA = 25 oC
-40 to 85 oC
Min. Typ . Max. Min . Max.
CIN Input Capacitance
4 10
10 pF
COUT Output Capacitance
9 pF
CPD Power Dissipation
Capacitance (note 1)
25 pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8 (per Flip-Flop)
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Conditions
V CC
( V)
Value
TA = 25 oC
Min. Typ. Max.
-40 to 85 oC
Min . Max.
Un it
VOLP Dynamic Low Voltage
VOLV Quiet Output (note 1, 2)
5.0
1.2 1.6
-1.6 -1.2
VIHD Dynamic High Voltage
Input (note 1, 3)
5.0
CL = 50 pF
3.5
V
VILD Dynamic Low Voltage
Input (note 1, 3)
5.0
1.5
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74VHCT574A.PDF ] | |
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