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STMicroelectronics |
® 74VHC273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 165 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE VOLP = 0.9V (Max.)
DESCRIPTION
The 74VHC273 is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP WITH
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
technology.
PRELIMINARY DATA
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC273M
74VHC273T
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs .
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
October 1999
1/10
74VHC273
INPUT EQUIVALENT CIRCUIT
TRUTH TABLE
CLEAR
L
H
H
H
X:Don’t Care
INPUTS
D
X
L
H
X
LOGIC DIAGRAMS
PIN DESCRIPTION
PIN No
1
2, 5, 6, 9,
12, 15, 16,
19
3, 4, 7, 8,
13, 14, 17,
18
11
10
20
S YM BO L
CLEAR
Q0 to Q7
NAME AND FUNCTION
Asyncronous Master
Reset (Active LOW)
Flip-Flop Outputs
D0 to D7 Data Inputs
CLOCK
GND
VCC
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
Ground (0V)
Positive Supply Voltage
CLOCK
X
OUTPUTS
Q
L
L
H
Qn
FUNCTION
CLEAR
NO CHANGE
Thislogic diagram has notbe used to esimate propagation delays
2/10
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