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STMicroelectronics |
® 74VHC238
3 TO 8 LINE DECODER
s HIGH SPEED: tPD =5.5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 238
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHC238 is an advanced high-speed
CMOS 3 TO 8 LINE DECODER fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
go high. If enable input G1 is held low or either
M1
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC238M
74VHC238T
G2A or G2B is held high, decoding function is
inhibited and all the 8 outputs go to low.
Three enable inputs are provided to ease
cascade connection and application of this
address decoders for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/8
74VHC238
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1, 2, 3
4, 5
6
15, 14, 13,
12, 11, 10,
9, 7
8
16
SYMBOL NAME AND FUNCT ION
A, B, C Address Inputs
G2A, G2B Enable Inputs
G1 Enable Input
Y0 to Y7 Outputs
GND
VCC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
ENABLE
G2B G2A
XX
XH
HX
LL
LL
LL
LL
LL
LL
LL
LL
X:Don’t Care
IN PUT S
G1 C
LX
XX
XX
HL
HL
HL
HL
HH
HH
HH
HH
SELECT
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
OUTPUTS
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
LL LL LL LL
LL LL LL LL
LL LL LL LL
HLLLLL LL
LHLLLL LL
LLHLLL LL
LLLHLL LL
L L L LHL LL
L L L L LHLL
L L L L LLHL
L L L L LL LH
LOGIC DIAGRAM
Thislogic diagram has notbe used to estimate propagation delays
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