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PDF 74VHC132 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC132 | |
| Descripción | Quad 2-Input NAND Schmitt Trigger | |
| Fabricantes | Fairchild Semiconductor | |
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December 2007
74VHC132
Quad 2-Input NAND Schmitt Trigger
Features
■ High Speed: tPD = 3.9ns (Typ.) at VCC = 5V
■ Power down protection is provided on all inputs
■ Low power dissipation: ICC = 2µA (Max.) at TA = 25°C
■ Low noise: VOLP = 0.8V (Max.)
■ Pin and function compatible with 74HC132
General Description
The VHC132 is an advanced high speed CMOS 2-input
NAND Schmitt Trigger Gate fabricated with silicon gate
CMOS technology. It achieves the high-speed operation
similar to Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. Pin configuration and
function are the same as the VHC00 but the inputs have
hysteresis between the positive-going and negative-
going input thresholds, which are capable of transform-
ing slowly changing input signals into sharply defined,
jitter-free output signals. Thus greater noise margin then
conventional gates is provided. An input protection
circuit ensures that 0V to 7V can be applied to the input
pins without regard to the supply voltage. This device
can be used to interface 5V to 3V systems and two
supply systems such as battery backup. This circuit
prevents device destruction due to mismatched supply
and input voltages.
Ordering Information
Order Number
Package
Number
Package Description
74VHC132M
74VHC132SJ
74VHC132MTC
M14A
M14D
MTC14
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74VHC132 Rev. 1.5.0
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
tPHL, tPLH Propagation Delay
CIN Input Capacitance
CPD Power Dissipation
Capacitance
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
Conditions
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
VCC = Open
(3)
TA = 25°C
Min. Typ. Max.
6.1 11.9
8.0 15.4
3.9 7.7
5.9 9.7
4 10
16
TA = –40°C
to +85°C
Min. Max.
1.0 14.0
1.0 17.5
1.0 9.0
1.0 11.0
10
Units
ns
pF
pF
Note:
3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
ICC (Opr.) = CPD • VCC • IIN + ICC / 4 (per gate)
©1995 Fairchild Semiconductor Corporation
74VHC132 Rev. 1.5.0
5
www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74VHC132.PDF ] | |
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