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74LVC4066 반도체 회로 부품 판매점

Quad bilateral switches



NXP Semiconductors 로고
NXP Semiconductors
74LVC4066 데이터시트, 핀배열, 회로
74LVC4066
Quad bilateral switch
Rev. 5 — 23 November 2011
Product data sheet
1. General description
The 74LVC4066 is a high-speed Si-gate CMOS device.
The 74LVC4066 provides four single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 (typical) at VCC = 2.7 V
6.5 (typical) at VCC = 3.3 V
6 (typical) at VCC = 5 V
Switch current capability of 32 mA
High noise immunity
CMOS low-power consumption
Direct interface TTL-levels
Latch-up performance exceeds 250 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Enable inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C


74LVC4066 데이터시트, 핀배열, 회로
NXP Semiconductors
74LVC4066
Quad bilateral switch
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC4066D 40 C to +125 C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LVC4066PW 40 C to +125 C TSSOP14 plastic thin small outline package; 14 leads;
body width 4.4 mm
74LVC4066BQ 40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1
4. Functional diagram
1 1Y
13 1E
4 2Y
5 2E
8 3Y
6 3E
11 4Y
12 4E
Fig 1. Logic symbol
1Z 2
2Z 3
3Z 9
4Z 10
mnb111
nY
nE
Fig 3. Logic diagram (one switch)
1
13 #
4
5#
8
6#
11
12 #
2
3
9
10
(a)
11
13 # X1
12
41
5 # X1
13
81
6 # X1
19
11 1
12 # X1
1 10
(b)
mnb112
Fig 2. Logic symbol (IEEE/IEC)
nZ
VCC
mna658
74LVC4066
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 23 November 2011
© NXP B.V. 2011. All rights reserved.
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