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74LVC3G17 반도체 회로 부품 판매점

Triple non-inverting Schmitt trigger with 5 V tolerant input



NXP Semiconductors 로고
NXP Semiconductors
74LVC3G17 데이터시트, 핀배열, 회로
74LVC3G17
Triple non-inverting Schmitt trigger with 5 V tolerant input
Rev. 03 — 31 January 2005
Product data sheet
1. General description
The 74LVC3G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device as translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC3G17 provides three non-inverting buffers with Schmitt-trigger action. It is
capable of transforming slowly changing input signals into sharply defined, jitter-free
output signals.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant input/output for interfacing with 5 V logic
s High noise immunity
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s ±24 mA output drive (VCC = 3.0 V)
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C.
3. Applications
s Wave and pulse shapers for highly noisy environments.


74LVC3G17 데이터시트, 핀배열, 회로
Philips Semiconductors
74LVC3G17
Triple non-inverting Schmitt trigger with 5 V tolerant input
4. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C.
Symbol Parameter
Conditions
tPHL, tPLH
CI
CPD
propagation delay
VCC = 1.8 V; CL = 30 pF;
input nA to output nY RL = 1 k
VCC = 2.5 V; CL = 30 pF;
RL = 500
VCC = 2.7 V; CL = 50 pF;
RL = 500
VCC = 3.3 V; CL = 50 pF;
RL = 500
VCC = 5.0 V; CL = 50 pF;
RL = 500
input capacitance
power dissipation
VCC = 3.3 V
capacitance per buffer
Min
-
-
-
-
-
-
[1] [2] -
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL × VCC2 × fo) = sum of outputs.
[2] The condition is VI = GND to VCC.
Typ Max Unit
5.6 -
ns
3.7 -
ns
3.8 -
ns
3.6 -
ns
2.7 -
ns
3.5 -
16.3 -
pF
pF
5. Ordering information
Table 2: Ordering information
Type number Package
Temperature range
74LVC3G17DP 40 °C to +125 °C
Name
TSSOP8
74LVC3G17DC 40 °C to +125 °C VSSOP8
74LVC3G17GT 40 °C to +125 °C XSON8
Description
Version
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
6. Marking
9397 750 14544
Product data sheet
Table 3: Marking codes
Type number
74LVC3G17DP
74LVC3G17DC
74LVC3G17GT
Marking code
V17
V17
V17
Rev. 03 — 31 January 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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