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PDF MH16S72BAMD-7 Data sheet ( Hoja de datos )
| Número de pieza | MH16S72BAMD-7 | |
| Descripción | 1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72BAMD -7,-8,-10
1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM
DESCRIPTION
The MH16S72BAMD is 16777216 - word by 72-bit
Synchronous DRAM module. This consists of
eighteen industry standard 8Mx8 Synchronous
DRAMs in TSOP and one industory standard
EEPROM in TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-7 100MHz 6.0ns(CL=3)
-8 100MHz 6.0ns(CL=3)
-10 100MHz
8.0ns(CL=3)
Utilizes industry standard 8M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD 1.0(-10))
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
APPLICATION
PC main memory
MIT-DS-0221-0.4
MITSUBISHI
ELECTRIC
( 1 / 55 )
29.Oct.1998
1 page  
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72BAMD -7,-8,-10
1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH16S72BAMD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
define basic commands
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0221-0.4
MITSUBISHI
ELECTRIC
( 5 / 55 )
29.Oct.1998
5 Page 
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72BAMD -7,-8,-10
1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
CKE CKE
Current State n-1 n
/S /RAS /CAS /WE Add
Action
SELF -
H X X X X X X INVALID
REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)
LHL
H H H X Exit Self-Refresh(Idle after tRC)
LHL
HHL
X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self-Refresh)
POWER
DOWN
H X X X X X X INVALID
L H X X X X X Exit Power Down to Idle
L L X X X X X NOP(Maintain Self-Refresh)
ALL BANKS H H X X X X X Refer to Function Truth Table
IDLE*2
H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
HLL
HLL
HLL
HLL
H H H X Enter Power Down
HHL
X ILLEGAL
H L X X ILLEGAL
L X X X ILLEGAL
L X X X X X X Refer to Current State = Power Down
ANY STATE H H X X X X X Refer to Function Truth Table
other than
H L X X X X X Begin CK0 Suspend at Next Cycle*3
listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3
L L X X X X X Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
MIT-DS-0221-0.4
MITSUBISHI
ELECTRIC
( 11 / 55 )
29.Oct.1998
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH16S72BAMD-7.PDF ] | |
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