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PDF MH16S64FFB-10L Data sheet ( Hoja de datos )
| Número de pieza | MH16S64FFB-10L | |
| Descripción | 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64FFB is 16777216 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 16Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
-10,10L 100MHz
CLK Access Time
(Component SDRAM)
8.0ns(CL=3)
Utilizes industry standard 16M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
MIT-DS-0280-0.1
MITSUBISHI
ELECTRIC
( 1 / 55 )
143
144
15. Jan.1999
1 page  
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
32
33
34
35
36-61
62
63
64-71
72
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
Checksum for bytes 0-62
Manufactures Jedec ID code per JEP-108E
Manufacturing location
73-90
91-92
93-94
95-98
99-125
126
127
128+
Manufactures Part Number
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
128MByte
N/A
N/A
N/A
N/A
option
rev 1
Check sum
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
MH16S64FFB-10
MH16S64FFB-10L
PCB revision
year/week code
serial number
option
66MHz
CL=2/3
open
20
00
00
00
00
00
01
53
1CFFFFFFFFFFFFFF
01
02
03
04
4D4831365336344646422D31302020202020
4D4831365336344646422D31304C20202020
rrrr
yyww
ssssssss
00
66
06
00
MIT-DS-0280-0.1
MITSUBISHI
ELECTRIC
( 5 / 55 )
15. Jan.1999
5 Page 
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
PRE -
CHARGING
ROW
ACTIVATING
WRITE RE-
COVERING
/S0 /RAS /CAS /WE Address
H X X XX
L H H HX
L H H L BA
L H L X BA,CA,A10
L L H H BA,RA
L L H L BA,A10
L L L HX
Op-Code,
LLLL
Mode-Add
H X X XX
L H H HX
L H H L BA
L H L X BA,CA,A10
L L H H BA,RA
L L H L BA,A10
L L L HX
Op-Code,
LLLL
Mode-Add
Command
Action
DESEL NOP(Idle after tRP)
NOP
NOP(Idle after tRP)
TBST
ILLEGAL*2
READ/WRITE ILLEGAL*2
ACT
ILLEGAL*2
PRE/PREA NOP*4(Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
DESEL NOP(Row Active after tRCD
NOP
NOP(Row Active after tRCD
TBST
ILLEGAL*2
READ/WRITE ILLEGAL*2
ACT
ILLEGAL*2
PRE/PREA ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT
ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
MIT-DS-0280-0.1
MITSUBISHI
ELECTRIC
( 11 / 55 )
15. Jan.1999
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH16S64FFB-10L.PDF ] | |
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