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PDF MC14022 Data sheet ( Hoja de datos )
| Número de pieza | MC14022 | |
| Descripción | Octal Counter | |
| Fabricantes | ON Semiconductor | |
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MC14022B
Octal Counter
The MC14022B is a four–stage Johnson octal counter with built–in
code converter. High–speed operation and spike–free outputs are
obtained by use of a Johnson octal counter design. The eight decoded
outputs are normally low, and go high only at their appropriate octal
time period. The output changes occur on the positive–going edge of
the clock pulse. This part can be used in frequency division
applications as well as octal counter or octal decode display
applications.
• Fully Static Operation
• DC Clock Input Circuit Allows Slow Rise Times
• Carry Out Output for Cascading
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4022B
• Triple Diode Protection on All Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 2.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14022BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14022B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14022BCP
PDIP–16
2000/Box
MC14022BD
SOIC–16
2400/Box
MC14022BDR2 SOIC–16 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14022B/D
1 page  
MC14022B
VDD
VSS
VDD
A
S1
VSS B
CLOCK Q0
ENABLE Q1
Q2
Q3
RESET Q4
Q5
Q6
Q7
CLOCK Cout
VSS
Vout
ID
EXTERNAL
POWER
SUPPLY
Output
Output
Sink Drive Source Drive
Outputs
Carry
(S1 to A)
Clock to desired
Output
(S1 to B)
Clock to Q5
thru Q7
(S1 to B)
S1 to A
VGS =
VDS =
VDD
Vout
– VDD
Vout – VDD
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
500 µF
PULSE
GENERATOR
fc
VDD
ID
0.01 µF
CERAMIC
CLOCK
ENABLE
RESET
CLOCK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cout
VSS CL CL CL CL CL CL CL CL CL
Figure 2. Typical Power Dissipation Test Circuit
APPLICATIONS INFORMATION
Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
CLOCK
R
C
CE MC14022B
Q0 Q1 • • • Q6 Q7
7 DECODED
OUTPUTS
R
C
CE MC14022B
Q0 Q1 • • • Q6 Q7
6 DECODED
OUTPUTS
FIRST STAGE
INTERMEDIATE STAGES
Figure 3. Counter Expansion
http://onsemi.com
5
R
C
CE MC14022B
Q1 • • • Q6 Q7
6 DECODED
OUTPUTS
LAST STAGE
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC14022.PDF ] | |
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