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PDF MC14020B Data sheet ( Hoja de datos )
| Número de pieza | MC14020B | |
| Descripción | 14-Bit Binary Counter | |
| Fabricantes | ON Semiconductor | |
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MC14020B
14-Bit Binary Counter
The MC14020B 14−stage binary counter is constructed with MOS
P−Channel and N−Channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of ripple−carry binary counter. The device
advances the count on the negative−going edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency−dividing circuits.
Features
• Fully Static Operation
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• Buffered Outputs Available from stages 1 and 4 thru 14
• Common Reset Line
• Pin−for−Pin Replacement for CD4020B
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
−0.5 to VDD + 0.5
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10 mA
PD Power Dissipation, per Package
(Note 1)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8−Second Soldering)
−55 to +125
−65 to +150
260
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
VSS 8
16 VDD
15 Q11
14 Q10
13 Q8
12 Q9
11 R
10 C
9 Q1
MARKING DIAGRAMS
16
14020BG
AWLYWW
1
SOIC−16
16
14
020B
ALYWG
G
1
TSSOP−16
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 9
1
Publication Order Number:
MC14020B/D
1 page  
MC14020B
500 mF
VDD
ID
0.01 mF
CERAMIC
PULSE
GENERATOR
C Q1
Q4
R Qn
VSS
CL
CL
CL
CLOCK
20 ns
90%
50%
10%
50% DUTY CYCLE
20 ns
VDD
VSS
Figure 1. Power Dissipation Test Circuit
and Waveform
PULSE
GENERATOR
VDD
C Q1
Q4
R Qn
VSS
CL
CL
CL
CLOCK
Q
tTLH
20 ns
tPLH
90%
50%
10%
90%
50%
10%
tWH
tTHL
20 ns
tPHL
Figure 2. Switching Time Test Circuit
and Waveforms
CLOCK
RESET
Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16,384
Figure 3. Timing Diagram
http://onsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC14020B.PDF ] | |
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