PDF MC-4R128CPE6C Data sheet ( Hoja de datos )

Número de pieza	MC-4R128CPE6C
Descripción	Direct Rambus DRAM RIMM Module 128M-BYTE 64M-WORD x 16-BIT
Fabricantes	NEC
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No Preview Available ! PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT MC-4R128CPE6C Direct RambusTM DRAM RIMMTM Module 128M-BYTE (64M-WORD x 16-BIT) Description The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for use in a broad range of applications including computer memory, personal computers, workstations, and other applications where high bandwidth and low latency are required. MC-4R128CPE6C modules consists of eight 128M Direct Rambus DRAM (Direct RDRAM™) devices (µPD488448). These are extremely high-speed CMOS DRAMs organized as 8M words by 16 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes). The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous, randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions per device. Features • 184 edge connector pads with 1mm pad spacing • 128 MB Direct RDRAM storage • Each RDRAM® has 32 banks, for 256 banks total on module • Gold plated contacts • RDRAMs use Chip Scale Package (CSP) • Serial Presence Detect support • Operates from a 2.5 V supply • Low power and powerdown self refresh modes • Separate Row and Column buses for higher efficiency • Over Drive Factor (ODF) support The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14807EJ2V0DS00 (2nd edition) Date Published August 2000 NS CP (K) Printed in Japan The mark 5 shows major revised points. © 2000 1 page MC-4R128CPE6C Module Connector Pad Description (1/2) Signal GND LCFM I/O — I LCFMN I LCMD I LCOL4..LCOL0 I LCTM I LCTMN I LDQA8..LDQA0 I/O LDQB8..LDQB0 I/O LROW2..LROW0 LSCK I I NC — RCFM I RCFMN I RCMD I RCOL4..RCOL0 I RCTM I RCTMN I RDQA8..RDQA0 I/O RDQB8..RDQB0 I/O RROW2..RROW0 I Type — RSL RSL VCMOS RSL RSL RSL RSL RSL RSL VCMOS — RSL RSL VCMOS RSL RSL RSL RSL RSL RSL Description Ground reference for RDRAM core and interface. 72 PCB connector pads. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command used to read from and write to the control registers. Also used for power management. Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices. Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices. Row bus. 3-bit bus containing control and address information for row accesses. Serial clock input. Clock source used to read from and write to the RDRAM control registers. These pads are not connected. These 24 connector pads are reserved for future use. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command Input used to read from and write to the control registers. Also used for power management. Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices. Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices. Row bus. 3-bit bus containing control and address information for row accesses. Preliminary Data Sheet M14807EJ2V0DS00 5 5 Page MC-4R128CPE6C Timing Parameters The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM data sheet (µPD488448) for detailed timing diagrams. Para- Description MIN. MAX. meter -845 -745 -653 tRC Row Cycle time of RDRAM banks - the interval between ROWA packets with 28 28 28 — ACT commands to the same bank. tRAS RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT 20 20 20 Note 2 64µs command and next ROWR packet with PRERNote1 command to the same bank. tRP Row Precharge time of RDRAM banks - the interval between ROWR packet with 8 8 8 — PRERNote1 command and next ROWA packet with ACT command to the same bank. tPP Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRER Note1 commands to any banks of the same device. 8 8 8— tRR RAS-to-RAS time of RDRAM device - the interval between successive ROWA 8 8 8 — packets with ACT commands to any banks of the same device. tRCD RAS-to-CAS Delay - the interval from ROWA packet with ACT command to 9 7 7— COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. tCAC CAS Access delay - the interval from RD command to Q read data. The equation for tCAC is given in the TPARM register. tCWD CAS Write Delay - interval from WR command to D write data. 8 8 8 12 6666 tCC CAS-to-CAS time of RDRAM bank - the interval between successive COLC 4 4 4 — commands. tPACKET Length of ROWA, ROWR, COLC, COLM or COLX packet. 4444 tRTR Interval from COLC packet with WR command to COLC packet which causes 8 8 8 — retire, and to COLM packet with bytemask. tOFFP The interval (offset) from COLC packet with RDA command, or from COLC 4444 packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for tOFFP is given in the TPARM register. tRDP Interval from last COLC packet with RD command to ROWR packet with PRER. 4 4 4— tRTP Interval from last COLC packet with automatic retire command to ROWR packet with PRER. 4 4 4— Notes 1. Or equivalent PREC or PREX command. 2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE. Units tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE Preliminary Data Sheet M14807EJ2V0DS00 11 11 Page

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