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LA5318V 반도체 회로 부품 판매점

Voltage-Dividing Voltage Generator for Multi-Voltage LCD Matrix Drive



Sanyo 로고
Sanyo
LA5318V 데이터시트, 핀배열, 회로
Ordering number : EN5670
Monolithic Linear IC
LA5318V
Voltage-Dividing Voltage Generator
for Multi-Voltage LCD Matrix Drive
Overview
The LA5318V is a variable voltage-dividing voltage
generator IC designed for driving LCD matrixes that
require multiple voltages.
Package Dimensions
unit: mm
3179A-SSOP20
[LA5318V]
Ambient temperature, Ta – °C
SANYO: SSOP20
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Maximum output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VEE max
IOUT max
Pd max
Topr
Tstg
VCC – VEE
V1 to V4
Conditions
Ratings
36
Internal*
330
–20 to +75
–30 to +125
Notes: *The value stipulated in the conditions listed in the separate document shall be used as the maximum output current.
1. Continuous operation (without damage to the device) is guaranteed in the above ranges.
2. The output pins V1 to V4 may be shorted to the power supply or to ground for periods of up to 1 ms. (When |VCC – VEE| < 35 V)
Operating Conditions at Ta = 25°C
Supply voltage
Input voltage
Input current
Parameter
Output current
Symbol
VEE
VREF
IINR
IOUTR
IOUT1, 2
IOUT3,4
Conditions
VCC – VEE
VCC – VREF: VREF VEE
INR
OUTR
V1, V2
V3, V4
Note: VCC and VEE must be set up so that |V1| and |VEE – V4| are at least 1 V.
Ratings
–35.5 to –6
–35 to –6
–0.2 to 0
0 to 50
–5 to +5
–10 to +5
Unit
V
mA
mW
°C
°C
Unit
V
V
mA
mA
mA
mA
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
82097HA(OT) No. 5670-1/4


LA5318V 데이터시트, 핀배열, 회로
LA5318V
Operating Characteristics at Ta = 25°C, VCC –VEE= –20 V, VREF = VEE, RX = 8R, BIN = OPEN
Parameter
Symbol
Conditions
Current drain
Output voltage ratio 1
Output voltage ratio 2
Output voltage ratio 3
Output voltage ratio 4
Output voltage ratio 5
Output voltage ratio 3
Internal resistance ratio 1
Internal resistance ratio 2
Internal resistance ratio 3
Internal resistance ratio 4
Resistance
Load regulation 1
Load regulation 2
Load regulation 3
Load regulation 4
Load regulation –1A
Load regulation –2A
Load regulation –3
Load regulation –4
Load regulation –1B
Load regulation –2B
OUTR pin saturation voltage
ICC, IEE
Ra1
Ra2
Rb1
Rb2
Rb3
Rb4
RX1
RX2
RX3
RX4
R
V1
V2
V3
V4
V1A
V2A
V3
V4
V1B
V2B
VOUTR
VCC – VEE= –20 V, RX = 8R, INR = VCC : VCC, VEE
V2/V1
(VREF – V3)/(VREF – V4)
VREF/V1
VREF/V2
VREF /(VREF – V3)
VREF /(VREF – V4)
RX1 – RX2
RX1 – RX3 Referenced to the resistance
RX1 – RX4 R between RX4 and VIN3
RX1 – VIN3
The value of R when the voltage across
RX4 and VIN3 is 0.5 V.
+0.1 mA < IOUT1 < +5 mA : V1
+0.1 mA < IOUT2 < +5 mA : V2
+0.1 mA < IOUT3 < +5 mA : V3
+0.1 mA < IOUT4 < +5 mA : V4
–0.5 mA < IOUT1 < –0.1 mA : V1
–0.5 mA < IOUT2 < –0.1 mA : V2
–10 mA < IOUT3 < –0.1 mA : V3
–10 mA < IOUT4 < –0.1 mA : V4
–5 mA < IOUT1 < –0.1 mA, BIN = GND : V1
–5 mA < IOUT2 < –0.1 mA, BIN = GND : V2
IOUT = 20 mA, VCC – INR = 2.7 : OUTR – VEE
Note: For IOUT, minus (–) indicates source current and plus (+) indicates sink current.
min
1.96
1.96
11.64
5.82
5.82
11.64
Ratings
typ
0.35
2.00
2.00
12.00
6.00
6.00
12.00
8
12
14
15
30
max
0.5
2.04
2.04
12.36
6.18
6.18
12.36
±20
±20
±20
±20
±20
±20
±20
±20
±20
±20
0.5
Unit
mA
k
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
V
Pin Assignment
Block Diagram
V1, V2 bias
control
VREF
control
(This circuit must be used with VRX1 VRX2 VRX3 VRX4.)
No. 5670-2/4




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