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74LV4066 반도체 회로 부품 판매점

Quad bilateral switches



Philips 로고
Philips
74LV4066 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74LV4066
Quad bilateral switches
Product specification
Supersedes data of 1996 Jan 01
IC24 Data Handbook
Philips
Semiconductors
1998 Jun 23


74LV4066 데이터시트, 핀배열, 회로
Philips Semiconductors
Quad bilateral switches
Product specification
74LV4066
FEATURES
Optimized for Low Voltage applications: 1.0V to 6.0V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25 °C.
Very low typ “ON” resistance:
25W at VCC – VEE = 4.5 V
35W at VCC – VEE = 3.0 V
60W at VCC – VEE = 2.0 V
Output capability: non-standard
ICC category: SSI
DESCRIPTION
The 74LV4066 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT4066.
The 74LV4066 has four independent analog switches. Each switch
has two input/output terminals (nY, nZ) and an active HIGH enable
input (nE). When nE is LOW the corresponding analog switch is
turned off.
The 74LV4066 has an on resistance which is dramatically reduced
in comparison with 74HCT4066.
FUNCTION TABLE
INPUTS
nE
L
H
NOTES:
H = HIGH voltage level
L = LOW voltage level
SWITCH
off
on
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf v 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPZH/tPZL
tPHZ/tPLZ
Turn “ON” time: nE to VOS
Turn “OFF” time: nE to VOS
CL = 15pF
RL = 1KW
VCC= 3.3V
CI Input capacitance
CPD Power dissipation capacitance per switch Notes 1, 2
CS Maximum switch capacitances
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; Cs = maximum switch capacitance in pF;
ȍ {(CL + CS) × VCC2 × Fo} = sum of the outputs.
VCC = supply voltage in V.
2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
TYPE NUMBER
74LV4066N
74LV4066D
74LV4066DB
74LV4066PW
PINS
16
16
16
16
PACKAGE
DIL
SO
SSOP
TSSOP
PACKAGES
MATERIAL
Plastic
Plastic
Plastic
Plastic
TYPICAL
10
13
3.5
11
8
UNIT
ns
ns
pF
pF
pF
CODE
SOT27-1
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1Y 1
1Z 2
2Z 3
2Y 4
2E 5
3E 6
GND 7
14 VCC
13 1E
12 4E
11 4Y
10 4Z
9 3Z
8 3Y
SV01669
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 4, 8, 11 1Y – 4Y Independent inputs/outputs
2, 3, 9, 10 1Z – 4Z Independent inputs/outputs
13, 5, 6, 12 1E to 4E Enable input (active HIGH)
7 GND Ground (0V)
14 VCC Positive supply voltage
1998 Jun 23
2 853-2077 19619




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