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PDF 74LS90 Data sheet ( Hoja de datos )

Número de pieza 74LS90
Descripción Decade and Binary Counters
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo

74LS90 datasheet


1. - Decade Counter - SN74LS90






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No Preview Available ! 74LS90 Hoja de datos, Descripción, Manual

June 1989
DM74LS90 DM74LS93
Decade and Binary Counters
General Description
Each of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the ’LS90 and divide-
by-eight for the ’LS93
All of these counters have a gated zero reset and the LS90
also has gated set-to-nine inputs for use in BCD nine’s com-
plement applications
To use their maximum count length (decade or four bit bina-
ry) the B input is connected to the QA output The input
count pulses are applied to input A and the outputs are as
described in the appropriate truth table A symmetrical di-
vide-by-ten count can be obtained from the ’LS90 counters
by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output QA
Features
Y Typical power dissipation 45 mW
Y Count frequency 42 MHz
Connection Diagrams (Dual-In-Line Packages)
TL F 6381 – 1
Order Number DM74LS90M or DM74LS90N
See NS Package Number M14A or N14A
TL F 6381 – 2
Order Number DM74LS93M or DM74LS93N
See NS Package Number M14A or N14A
C1995 National Semiconductor Corporation TL F 6381
RRD-B30M105 Printed in U S A

1 page




74LS90 pdf
’LS93 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
Parameter
Conditions
Min Typ Max Units
(Note 1)
IIL
Low Level Input
VCC e Max VI e 0 4V
Reset
Current
A
b0 4
b2 4
mA
B b1 6
IOS Short Circuit
Output Current
VCC e Max (Note 2)
b20
b100
mA
ICC Supply Current
VCC e Max (Note 3)
9 15 mA
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3 ICC is measured with all outputs open both RO inputs grounded following momentary connection to 4 5V and all other inputs grounded
Note 4 QA outputs are tested at IOL e max plus the limit value of IIL for the B input This permits driving the B input while maintaining full fan-out capability
’LS93 Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL e 2 kX
CL e 15 pF
CL e 50 pF
Min Max Min Max
fMAX
tPLH
Maximum Clock
Frequency
Propagation Delay Time
Low to High Level Output
A to QA
B to QB
A to QA
32 20
16 10
16 20
tPHL
Propagation Delay Time
High to Low Level Output
A to QA
18 24
tPLH
Propagation Delay Time
Low to High Level Output
A to QD
70 85
tPHL
Propagation Delay Time
High to Low Level Output
A to QD
70 90
tPLH
Propagation Delay Time
Low to High Level Output
B to QB
16 23
tPHL
Propagation Delay Time
High to Low Level Output
B to QB
21 30
tPLH
Propagation Delay Time
Low to High Level Output
B to QC
32 37
tPHL
Propagation Delay Time
High to Low Level Output
B to QC
35 44
tPLH
Propagation Delay Time
Low to High Level Output
B to QD
51 60
tPHL
Propagation Delay Time
High to Low Level Output
B to QD
51 70
tPHL Propagation Delay Time SET-0 to
High to Low Level Output
Any Q
40 52
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5

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