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PDF 74LS193 Data sheet ( Hoja de datos )
| Número de pieza | 74LS193 | |
| Descripción | Synchronous 4-Bit Binary Counter with Dual Clock | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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 1. - 4-Bit Up/Down Binary Counter  Hay una vista previa y un enlace de descarga de 74LS193 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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September 1986
Revised March 2000
DM74LS193
Synchronous 4-Bit Binary Counter with Dual Clock
General Description
The DM74LS193 circuit is a synchronous up/down 4-bit
binary counter. Synchronous operation is provided by hav-
ing all flip-flops clocked simultaneously, so that the outputs
change together when so instructed by the steering logic.
This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple-
clock) counters.
The outputs of the four master-slave flip-flops are triggered
by a LOW-to-HIGH level transition of either count (clock)
input. The direction of counting is determined by which
count input is pulsed while the other count input is held
HIGH.
The counter is fully programmable; that is, each output may
be preset to either level by entering the desired data at the
inputs while the load input is LOW. The output will change
independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modi-
fying the count length with the preset inputs.
A clear input has been provided which, when taken to a
high level, forces all outputs to the low level; independent
of the count and load inputs. The clear, count, and load
inputs are buffered to lower the drive requirements of clock
drivers, etc., required for long words.
These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in
width to the count down input when the counter underflows.
Similarly, the carry output produces a pulse equal in width
to the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.
Features
s Fully independent clear input
s Synchronous operation
s Cascading circuitry provided internally
s Individual preset each flip-flop
Ordering Code:
Order Number
DM74LS193M
DM74LS193N
Package Number
Package Description
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006406
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
From (Input)
To (Output)
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Count Up
to Carry
Count Up
to Carry
Count Down
to Borrow
Count Down
to Borrow
Either Count
to Any Q
Either Count
to Any Q
Load to
Any Q
Load to
Any Q
Clear to
Any Q
RL = 2 kΩ
CL = 15 pF
Min Max
25
26
CL = 50 pF
Min Max
20
30
24 36
24 29
24 32
38 45
47 54
40 41
40 47
35 44
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74LS193.PDF ] | |
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