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System Logic Semiconductor |
SL74LS161
Synchronous 4 Bit Counters; Binary,
Direct Reset
This synchronous, presettable counter features an internal carry
look-ahead for application in high-speed counting designs.
Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change conicident with each other
when so instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting spikes that
are normally associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising (positive-
going) edge of the clock input wave form.
This counter is fully programmable; that is the outputs may be
preset to either level. As presetting is synchronous setting up a low
level at the load input disables the counter and causes the outputs to
agree with the setup data after the next clock pulse regardless of the
levels of the enable inputs.
The carry look-ahead circuitry provides for cascading counters for
n-bit synchronous applications without additional gating. Instrumental
in accomplishiing this function are two counter-enable inputs and a
ripple carry output. Both countenable inputs (ENABLE P and
ENABLE T) must be high to count, and ENABLE T is fed forward to
enable the ripple carry output. The ripple carry output thus enabled
will produce a high-level output pulse with a duration approximately
equal to the high level portion of the QA output. The high-level
overflow ripple carry pulse can be enable successive cascaded
stages. Transitions at the ENPor ENT are allowed regardless of the
level of the clock input.
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• Diode-Clamped Inputs
ORDERING INFORMATION
SL74LS161N Plastic
SL74LS161D SOIC
TA = 0° to 70° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
SLS
System Logic
Semiconductor
PIN 16 =VCC
PIN 8 = GND
SL74LS161
FUNCTION TABLE
Inputs
Outputs
Reset Load Enable Enable Clock Q0 Q1 Q2 Q3
PT
Function
LX
X
X
X L L L L Reset to “0”
HL X
X
P0 P1 P2 P3 Preset Data
HH
X
L
No change
No count
HH
L
X
No change
No count
HH
H
H
Count up
Count
HX
X
X
No change
No count
X=don’t care
P0,P1,P2,P3 = logic level of Data inputs
Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
Tstg
Parameter
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Value
7.0
7.0
5.5
-65 to +150
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Unit
V
V
V
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIH
VIL
IOH
IOL
fclock
tw(clock)
tw(reset)
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock frequency
Width of clock pulse
Width of reset pulse
Data inputs P0, P1, P2, P3
tsu Setup time
Enable P or T
Load
th Hold time at any input
TA Ambient Temperature Range
Min Max Unit
4.75 5.25
V
2.0 V
0.8 V
-0.4 mA
8.0 mA
0 25 MHz
25 ns
20 ns
20
20 ns
20
3 ns
0 +70 °C
SLS
System Logic
Semiconductor
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