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ST Microelectronics |
74LCX574
OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s 5V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED:
fMAX = 150 MHz (MIN.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
SOP
TSSOP
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LCX574MTR
74LCX574TTR
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX574 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The Output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
Rev. 5
1/13
74LCX574
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1
2, 3, 4, 5, 6,
7, 8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
SYMBOL
OE
D0 to D7
NAME AND FUNCTION
3-State Output Enable
Input (Active LOW)
Data Inputs
Q0 to Q7 3-State Outputs
CK
GND
VCC
Clock Input (LOW-to-HIGH
Edge Triggered)
Ground (0V)
Positive Supply Voltage
Figure 3: Logic Diagram
Table 3: Truth Table
INPUT
OE CK
HX
L
L
L
X : Don’t Care
Z : High Impedance
D
X
X
L
H
OUTPUT
Q
Z
NO CHANGE
L
H
This logic diagram has not be used to estimate propagation delays
2/13
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