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PDF WM8181 Data sheet ( Hoja de datos )
| Número de pieza | WM8181 | |
| Descripción | 12-bit 2MSPS Serial Output CIS/CCD Digitiser | |
| Fabricantes | Wolfson Microelectronics plc | |
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WM8181
12-bit 2MSPS Serial Output CIS/CCD Digitiser
Advanced Information, January 2000, Rev 3.0
DESCRIPTION
The WM8181 is a 12-bit resolution, 2MSPS single channel
image digitiser which is designed for easy interface to either
CIS or CCD linear image sensors. Data is output in serial
mode. The applied clock frequency (MCLK) equals the bit
rate of the data output. The sample rate of the WM8181 can
be either 1/12th or 1/16th of the applied master clock
frequency.
The device can be configured for either single-ended or
differential input operation. In single ended input mode, a
reset clamp voltage can be applied to the analogue signal,
under the control of a digital signal at the CLAMP pin. The
WM8181 will accept either positive or negative-going video
signals at any voltage between AGND and AVDD. The ADC
references are internally generated. The range of these
references may be derived internally using a bandgap
generator or externally using the VREFIN pin.
The WM8181 is powered from either 3.3V or 5V single
supplies. The device may also be powered from split 5V
and 3.3V dual supplies. Typically, the WM8181 consumes
23mA supply current in normal operation. When the device
is powered down, the supply current falls to less than 1µA.
The WM8181 is available in a 16-pin wide-body SOIC
package.
FEATURES
• 12-bit 2MSPS ADC
• No missing codes
• Serial output
• Simple clocking
• Internal or external ADC reference range control
• Accepts positive or negative video
• Rail to rail input range
• Reset-level clamp switch
• 3.3V or 5V single supplies
• 5V/3.3V dual supplies
• 23mA supply current
• 16-pin wide body SOIC package
APPLICATIONS
• USB bus powered scanners
• Flatbed scanners
• Sheetfeed scanners
• Contact image sensors (CIS)
• Linear CCDs
BLOCK DIAGRAM
AVDD
(16)
VSMP
(12)
MCLK
(13)
WM8181
PD
TIMING AND
POWER DOWN CONTROL
VINP (4)
VINM (5)
CLAMP (11)
VREFIN (3)
SAMPLE/
HOLD
ADC
0.8*VDD +
-
x1
1.5V
BAND-
GAP
VRT/VRB
GENERATOR
PARALLEL
TO
12 SERIAL
(15) DVDD
(14) DOUT
(10) DGND
(1) (2)
AGND1 AGND2
(7)
VRT
(6)
VRB
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
Advanced Information data sheets contain
preliminary data on new products in the
preproduction phase of development.
Supplementary data will be published at a
later date.
2000 Wolfson Microelectronics Ltd.
1 page  
Advanced Information
WM8181
TEST CHARACTERISTICS
AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
DIGITAL SPECIFICATION
Digital Inputs
High level input voltage
VIH
Low level input voltage
VIL
High level input current
Low level input current
Input capacitance
Digital Outputs
High level output voltage
Low level output voltage
High impedance output current
OVERALL SYSTEM SPECIFICATION
Supply Currents
Total analogue supply current –
active
Total digital supply current –
active
Supply current – disabled
TEST
CONDITIONS
MIN
0.8 ∗ DVDD
IOH = 1mA
IOL = -1mA
DVDD - 0.5
AVDD = DVDD = 5V
AVDD = DVDD = 3.3V
AVDD = DVDD = 5V
AVDD = DVDD = 3.3V
AVDD = DVDD = 5V
AVDD = DVDD = 3.3V
TYP
MAX
UNIT
V
0.2 ∗ DVDD V
<1 µA
<1 µA
5 pF
V
0.5 V
<1 µA
21 mA
19 mA
2 mA
1 mA
<1 µA
<1 µA
MCLK
VSMP
DOUT
tPER
tMCLKH tMCLKL
tVSMPSU
tVSMPH
SAMPLE n
tPD
n-2 D[11]
n-2 D[10]
n-2 D[9]
Figure 1 Clock Inputs and Data Output
TEST CHARACTERISTICS
AVDD = DVDD = 2.97 to 3.63V and 4.5 to 5.5V, AGND1 = AGND2 = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
Maximum MCLK period
MCLK high
MCLK low
VSMP data set-up time
VSMP data hold time
MCLK to DOUT
propagation delay
tPER
tMCLKH
tMCLKL
tVSMPSU
tVSMPH
tPD
AVDD = DVDD = 5V
MCLK to DOUT
propagation delay
tPD AVDD = DVDD = 3.3V
Note: Parameters are measured at 50% of the rising/falling edge.
MIN
41.7
16
16
10
10
TYP
10
15
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 January 2000
5
5 Page 
Advanced Information
CCD SCANNER
WM8181
The differential nature of the WM8181 allows it to interface as easily to CCD sensors as to CIS. The
negative going video simply requires that the VINP and VINM pins are swapped over so that the
video signal is applied to VINM and the reference voltage is applied to VINP. The d.c. level of the
CCD output must lie within the input limits of the WM8181. A level shifter may be required to ensure
this. See Figure 8.
LEVEL SHIFT
DEPENDENT ON
VOUT DC LEVEL
BLACK
REFERENCE
LEVEL
VOUT
LEVEL
SHIFT
CCD
SENSOR
WM8181
VINP
MCLK
VSMP
DOUT
VINM
VREFIN
CLAMP
VRT VRB
SYSTEM
ASIC
SET VOLTAGE TO MATCH
VPP FROM SENSOR.
Figure 8 d.c. Coupled Negative Video
USING THE INTERNAL CLAMP
When using a CCD it is recommended that the designer use a.c. (capacitive) coupling between the
CCD output buffer and the input to the WM8181, shown in Figure 9. A CCD sensor has a negative
going video signal superimposed on a d.c. voltage of around 6V. The series capacitor between the
CCD buffer and the input to the WM8181 removes this large d.c. voltage while still allowing the video
signal through.
VOUT
CCD
SENSOR
4.7k
4.7k
220n
WM8181
VINP
MCLK
VSMP
DOUT
200p
VINM
CLAMP
VREFIN VRT VRB
SYSTEM
ASIC
SET VOLTAGE TO MATCH
VPP FROM SENSOR.
Figure 9 a.c. Coupled Negative Video
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 January 2000
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet WM8181.PDF ] | |
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