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PDF WARP11 Data sheet ( Hoja de datos )
| Número de pieza | WARP11 | |
| Descripción | WEIGHT ASSOCIATIVE RULE PROCESSOR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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W.A.R.P. 1.1
WEIGHT ASSOCIATIVE RULE PROCESSOR
ADVANCED DATA
High Speed Rules Processing
Antecedent Membership Functions with any
Shape
Up to 256 Rules (4 Antecedents,1
Consequent)
Up to 16 Input Configurable Variables
Up to 16 Membership Functions for an Input
Variable
Up to 16 Output Variables
Up to 128 Membership Functions for all
Consequents
MAX-DOT Inference Method
Defuzzification on chip
Software Tools and Emulators Availability
100-pin CPGA100 Ceramic Package
84-lead Plastic Leaded Chip Carrier package
GENERAL DESCRIPTION
W.A.R.P. is a VLSI Fuzzy Logic controller whose
architecture arises from the need of realizing an
integrated structure with high inferencing perform-
ances and flexibility. To get those results a modular
architecture based on a set of parallel memory
blocks has been implemented.
In order to obtainhigh performances W.A.R.P. uses
different data representations during the various
phases of the computational cycle, so that it is
always operating on the optimal data repre-
sentation. A vectorial characterization has been
adopted for the Antecedent Membership Func-
tions. W.A.R.P. exploits a SGS-THOMSON pat-
ented strategy to store the AntecedentMembership
CPGA 100
PLCC84
Figure 1. Logic Diagram
MCLK VS S VDD
FIN
S YNC
8
10
O0-O9
4
I0-I7 W.A.R.P.
O CNT0- O CNT3
3 1.1
STB
EPA 0- E PA2
NP
10
A0-A9
EP
CHM OFL PRS T
Table 1. W.A.R.P. Configuration Settings
Number of Inputs
Standard Rule Format
Rules Number
Antecedent’s MFs Number
Consequent’s MFs Number
Input Data Resolution
Output Data Resolution
Configurable [1..8]
4 Antecedents, 1 Consequent [or subsets]
Max 256 Rules in the 4 Antecedent, 1 Consequent format
Configurable [up to 16 for an input variable]
Max 256 for all outputs variables
8 bit
8 bit
May 1996
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
1/19
1 page  
W.A.R.P.1.1
add7 add6 add5 add4 add3 add2 add1 add0
cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0
cs2 cs1 cs0 add6 add5 add4 add3 add2 add1 add0
A9 A0
This resulting word allows to identify the appropri-
ate memory [cs2-cs0] and its respective address
[add6-add0] where the relative I0-I7 are to be
stored.
When the CHM pin is high, during the off-line
phase, W.A.R.P. generates the addresses for its
internal memories and send those addresses to the
single external memory support where data (.dat
file) are located. These addresses, which are sent
by means of the EPA0-EPA2 and A0-A9 (EPA0
MSB, A9 LSB) output pins, allow to identify the
data (on the EPROM) that have be loaded in
W.A.R.P. internal memories.
In on-line mode A0-A9 are not used.
I0-I7: During the off-line phase these 8 data input
pins accept the microcode configuration and data
to be written into the internal memories. The ante-
cedent memory word size is 64 bits, so it is neces-
sary to give each word 8 bits at a time. In the same
way are written the words of consequent memory
and of program memory.
In on-line mode this bus carries the input variables
to W.A.R.P.. Input values have a resolution of 6 or
7 bits in accordance with the configuration setting.
PRST: This is the restart pin of W.A.R.P.. It is
possible to restart the work during the computation
(on-line phase) or before the writing of internal
memories (off-line phase). In both cases it must be
put low at least for a clock period.
FIN: During the on-line phase it will start the run-
time acquisition cycle. This pin is activated by
providing a positive pulse for a time no lower than
an entire clock period. When all expected inputs
have been processed, a new FIN pulse must be
sent to activate a new process.
OFL: When this pin is high, the chip is enabled to
load data in the internal RAMs (off-line phase). It
must be low when the fuzzy controller is waiting for
input values and during the processing phase (on-
line phase).
CHM:This pin, which is used only during the off-line
phase, determines the charge mode. CHM is not
present in W.A.R.P. 1.0 release.
When CHM is low the addresses of the internal
memory locations where data have to be stored
must be sent to W.A.R.P. from the outside by
means of the input pins A0-A9.
When CHM is high W.A.R.P. automatically gener-
ates the addresses of its internal memories and
manages the EPROMs reading by means of the
addresses contained in EPA0-EPA2 and A0-A9
output pins (13 bits).
TE: For testing purpose only. It must be connected
to VSS.
MTE: For testing purpose only. It must be con-
nected to VSS.
MCLK: This is the input master clock whose fre-
quency can reach up to 40MHz (MAX).
During the off-line phase with CHM high, the
DCLK signal with a frequency of MCLK/32 is gen-
erated in order to drive the downloading phase
timing.
EPA0-EPA2: During the off-line phase and in cor-
respondencewith CHM high, these output pins are
joined (as MSB) to A0-A9 to obtaine the complete
address of the memory support where to read the
data to be loaded in W.A.R.P. internal memories.
EPA0-EPA2 are not used when CHM is low or in
W.A.R.P. 1.0 release.
O0-O9: These pins carry out the output values.
When the STB (strobe pin) is high, one output
variable can be read by external devices (in on-line
mode). The resolution of output variables is 1024
points (10 bits). If there are more than one output,
the output variables are calculated one by one and
they are provided in the sequence stabilized during
the editing phase (see W.A.R.P.-SDT User Man-
ual).
OCNT0-OCNT3: This 4 bit output bus provides the
output variables with a progressive number during
the on-line phase. As a consequenceit is possible
to know to which variable correspond the data that
are on the output data bus (O0-O9). The dimension
of OCNT bus is connected with the maximum
number of output variables (16).
STB: The strobe pin enables the user to utilize the
output. When this pin is high it indicates that a new
output variable has been calculated and it is ready
on the output bus (O0-O9). This signal synchro-
nizes the external devices and in particular the
interfaces with the controlled processes (on-line
mode).
EP: This signal low indicates that the processing
of all the rules has been completed.
NP: This output pin indicates that a new process
can start. NP is automatically set low before the
last output has been calculated, so that it is possible
to start a new data acquisition before (with a new
FIN) the computation is terminated.
5/19
5 Page 
W.A.R.P.1.1
W.A.R.P. TIMING TABLES
Off-line Phase Timing (Internal RAMs Loading with Charge Mode ”0”)
OFL
F IN d e te c tio n
D ATA 0 a c q u is iti o n
D ATA 1 a c q u is iti o n
D ATA n a c q u is it io n
MC LK
F IN
I0 -I6
D ATA 0
TA C Q
D ATA 1
D ATA n
NP
EP
TA C Q = 2 0 0 n s fo r a c o n fig u r a tio n w ith 1 6 in p u t s , 8 o u tp u t s , 2 8 r u le s
Timing Table Description: OFF-LINE phase (CHM ”0”)
- CHM [INPUT] low will enable the ’manual downloading’ by specifying the address and data to be loaded
into W.A.R.P..
- MCLK [INPUT] must be connected with the external synchronization signal.
- PRST [INPUT] must be set high to enable the device.
- OFL [INPUT] must be set high to enable the configurationloading phase into the internal RAMs of W.A.R.P..
- The input to be written into the internal memories at the address specified in A0-A9 must be put into I0-I7
bus .
- SYNC [OUTPUT] will be provided to synchronize input data (I0-I7,A0-A9) coming from an external
database. SYNC frequency is MCLK/32 with a phase delay of tCSP ns . W.A.R.P. stores the data present
on input buses at the rising edge of MCLK, returns a SYNC pulse after tCSP ns indicating that is waiting for
new data and address that must be given within next 31MCLK pulses. Afterwards W.A.R.P. stores the data
on input buses and restores a new SYNC pulse.
W.A.R.P. stores the data situated in I0-I7 and the addresses A0-A9 into its internal registers.
Figure 8. Block Diagram for W.A.R.P. downloading (CHM ”0”)
11/19
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| PDF Descargar | [ Datasheet WARP11.PDF ] | |
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