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100MHZ CLOCK FOR SIS CHIPSET



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W83194R-81 데이터시트, 핀배열, 회로
W83194R-81
100MHZ CLOCK FOR SIS CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-81 is a Clock Synthesizer for SiS chipset. W83194R-81 provides all clocks required
for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium and also provides 16
different frequencies of CPU clocks frequency setting. All clocks are externally selectable with
smooth transitions. The W83194R-81 makes SDRAM in synchronous or asynchronous frequency
with CPU clocks.
The W83194R-81 provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and W83194R-81 provides the 0.25%, 0.5% center type spread spectrum to reduce
EMI.
The W83194R-81 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium, PentiumPro, AMD and Cyrix CPUs with I2C.
3 CPU clocks
13 SDRAM clocks for 3 DIMMs
6 PCI synchronous clocks.
Optional single or mixed supply:
(Vdd = Vddq4=Vddq3 = Vddq2b = 3.3V, Vddq2=2.5V) or
(Vdd = Vddq4=Vddq3 = 3.3V, Vddq2=Vdq2b = 2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
SDRAM frequency synchronous or asynchronous to CPU clocks
Smooth frequency switch with selections from 66 to 133mhz(including 90MHz)
I2C 2-Wire serial interface and I2C read back
0.25%, 0.5% center type spread spectrum to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
48-pin SSOP package
Publication Release Date: Dec. 1998
- 1 - Revision 0.20


W83194R-81 데이터시트, 핀배열, 회로
W83194R-81
3.0 BLOCK DIAGRAM
SEL24_14#
Xin
Xout
*FS(0:2) 3
*MODE
CPU3.3_2.5#
*SD_SEL#
SDRAM_STOP#
CPU_STOP#
PCI_STOP#
PD#
*SDAT
A*SCLK
PLL2
¡Ò2
XTAL
OSC
PLL1
Spread
Spectrum
STOP
CPU_STOP#
LATCH
5
POR
PCI
clock STOP
Divder
Contro
l Logic
Config
. Reg.
PCI_STOP#
PRELIMINARY
48MHz
SIO
REF(0:2)
3
IOAPIC
CPUCLK(0:2)
3
SDRAM(0:12)
13
PCICLK(0:4)
5
PCICLK_F
4.0 PIN CONFIGURATION
Vdd
REF0/ *MODE
Vss
Xin
Xout
Vddq4
PCICLK_F/ *FS1
PCICLK0/ *FS2
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq4
SDRAM12
Vss
*CPU_STOP#/SDRAM11
*PCI_STOP#/SDRAM10
Vddq3
*SDRAM_STOP#/SDRAM 9
*PD#/SDRAM 8
Vss
*SDATA
*SDCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 Vddq2
47 IOAPIC
46 REF1/ *SD_SEL#
45 Vss
44 REF2/CPU3.3_2.5#
43 CPUCLK0
42 Vddq2b
41 CPUCLK1
40 CPUCLK
39 2Vss
38 SDRAM 0
37 SDRAM 1
36 Vddq3
35 SDRAM 2
34 SDRAM 3
33 Vss
32 SDRAM 4
31 SDRAM 5
30 Vddq3
29 SDRAM 6
28 SDRAM 7
27 Vss
26 48MHz/*FS0
25 SIO/*SEL24_14#
Publication Release Date: Dec. 1998
- 2 - Revision 0.20




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