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Winbond |
W83194BR-97
200MHZ CLOCK FOR CAMINO CHIPSET
1.0 GENERAL DESCRIPTION
The W83194BR-97 is a Clock Synthesizer for Intel Camino 820 chipset. W83194BR-97 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 sets of different
frequencies of CPU, PCI, 3V66, IOAPIC clocks or stepless frequecies programming by M/N value via
I2C registers. All clocks are externally selectable with smooth transitions.
The W83194BR-97 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.5% and 0.25% center type spread spectrum to reduce EMI.
The W83194BR-97 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU
CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5%
duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns
slew rate.
2.0 PRODUCT FEATURES
• 2 CPU clock outputs
• One CPU/2 output as reference input to DRCG
• 3 3V66 clock outputs
• 3 IOAPIC clock outputs
• 8 PCI synchronous clocks.
• Optional single or mixed supply:
(VddQ2 = VddQ3 = 3.3V or VddQ3=3.3V, VddQ2=2.5V)
• CPU to 3V66 offset 0 to 1.5 ns
• 3V66 to PCI offset 1.5 to 4.0 ns
• Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.8 to 200MHz
• Stepless programmable frequencies by I2C register9 ~ register12
• I2C 2-Wire serial interface and I2C read back
• 0.5% and 0.75% center type spread spectrum
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 48 MHz pins for USB
• 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: Dec. 1999
- 1 - Revision 0.35
3.0 PIN CONFIGURATION
VSSR
REF0
REF1/*SEL24_48#
VDDR
Xin
Xout
VSSP
PCICLK_F/ *FS0
PCICLK1/ *FS1
VDDP
PCICLK2/ *FS2
PCICLK3/ *FS3
VSSPCI
PCICLK4
PCICLK5
VDDP
PCICLK6
PCICLK7
VSSPCI
PCICLK8
PCICLK9
PCICLK10
VDDPCI
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W83194BR-97
PRELIMINARY
48 VddA
47 IOAPIC0
46 IOAPIC1
45 VSSA
44 IOAPIC2
43 VDDC/2
42 CPU/2
41 VSSC/2
40 CPUCLK0
39 VDDCPU
38 CPUCLK1
37 CPUCLK2
36 VSSCPU
35 VDD66
34 3V66-0
33 3V66-1
32 3V66-2
31 VSS66
30 *SDATA
29 *SDCLK
28 VDD48
27 48MHz/ *FS4
26 24_48MHz/FREQ_APIC*
25 VSS48
Publication Release Date: Dec. 1999
- 2 - Revision 0.35
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