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PDF W83194BR-39B Data sheet ( Hoja de datos )

Número de pieza W83194BR-39B
Descripción STEP-LESS 3-DIMM CLOCK
Fabricantes Winbond 
Logotipo Winbond Logotipo



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W83194BR-39B
STEP-LESS 3-DIMM CLOCK
1.0 GENERAL DESCRIPTION
The W83194BR-39B is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium II or Pentium III. W83194BR-39B provides 64 CPU/PCI
frequencies which are selectable with smooth transitions by hardware or software. W83194BR-39B
also provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194BR-39B provides step-less frequency programming by controlling the VCO freq. and the
programmable PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the
RESET# pin will output 4ms pulse signal.
The W83194BR-39B accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at
±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency
selection through I2C interface. The device meets the Pentium power-up stabilization, which requires
CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA,
PCI, CPU, DIMM) is not recommend.
2.0 PRODUCT FEATURES
Supports PentiumII and !!! CPU with I2C.
2 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMMs
6 PCI synchronous clocks
One IOAPIC clock for multiprocessor support
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VddL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 250ps skew among PCI clocks
< 5ns propagation delay SDRAM from buffer input
Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 66 MHz to 200 MHz CPU
Step-less frequency programming by controlling the VCO freq. and the clock output divisor ratio
I2C 2-Wire serial interface and I2C read back
±0.25% or ±0.5% spread spectrum function to reduce EMI in freq. table mode
Programmable spread spectrum in the M/N step-less mode
Programmable registers to enable/stop each output and select modes
MODE pin for power Management
RESET# out when watch dog timer time out
One 48 MHz for USB & one 24 MHz for super I/O
Publication Release Date: June 2000
- 1 - Revision 0.46

1 page




W83194BR-39B pdf
W83194BR-39B
5.0 FREQUENCY BY HARDWARE
PRELIMINARY
FS3 FS2 FS1 FS0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CPU(MHz)
80.00
75.00
83.30
66.82
103.00
112.00
68.01
100.23
120.00
115.00
120.00
105.00
140.00
155.00
124.00
133.30
SDRAM(MHz)
80.00
75.00
83.30
66.82
103.00
112.00
68.01
100.23
120.00
115.00
120.00
105.00
140.00
155.00
124.00
133.30
PCI(MHz)
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
30.00
38.33
40.00
35.00
35.00
38.75
31.00
33.30
Publication Release Date: June 2000
- 5 - Revision 0.46

5 Page





W83194BR-39B arduino
W83194BR-39B
2 1 - Reserved
1 1 - Reserved
0 1 - Reserved
7.2.6 Register 5: Reserved Register
Bit @PowerUp Pin
7 1 - Reserved
6 0 - Reserved
5 0 - Reserved
4 1 - Reserved
3 0 - Reserved
2 0 - Reserved
1 1 - Reserved
0 1 - Reserved
Description
7.2.7 Register 6~11: M/N step-less mode control registers
7.2.12 Register 11: Winbond Chip ID Register (Read Only)
Bit @PowerUp Pin
Description
7 0 - Winbond Chip ID
6 1 - Winbond Chip ID
5 1 - Winbond Chip ID
4 0 - Winbond Chip ID
3 0 - Winbond Chip ID
2 0 - Winbond Chip ID
1 1 - Winbond Chip ID
0 0 - Winbond Chip ID
7.2.13 Register 12: Winbond Chip ID Register (Read Only)
Bit @PowerUp Pin
7 0 - Winbond Chip ID
6 1 - Winbond Chip ID
5 0 - Winbond Chip ID
4 1 - Winbond Chip ID
3 0 - Winbond Version ID
Description
PRELIMINARY
- 11 -
Publication Release Date: June 2000
Revision 0.46

11 Page







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