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PDF EX128-FTQ100 Data sheet ( Hoja de datos )
| Número de pieza | EX128-FTQ100 | |
| Descripción | ex Family FPGAs | |
| Fabricantes | Actel | |
| Logotipo |  |
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eX Automotivewww.DataSheet4U.com Family FPGAs
v3.2
™
ue
Specifications
• 3,000 to 12,000 Available System Gates
• Maximum 512 Flip-Flops (Using CC Macros)
• 0.22 µm CMOS Process Technology
• Up to 132 User-Programmable I/O Pins
Features
• 250 MHz Internal Performance, Low-Power Antifuse
FPGA
• Advanced Small-Footprint Packages
• Pin-to-Pin Compatibility with eX Commercial- and
Industrial-Grade Devices
• Hot-Swap Compliant I/Os
• Single-Chip Solution
• Nonvolatile
• Live on Power-Up
• No Power-Up/Down Sequence Required for Supply
Voltages
• Configurable Weak Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
• Individual Output Slew-Rate Control
• 2.5 V and 3.3 V I/Os
• Software Design Support with Actel Designer and
Libero® Integrated Design Environment (IDE)
Tools
• Up to 100% Resource Utilization with 100% Pin
Locking
• Deterministic Timing
• Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• FuseLock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Product Profile
Device
eX64
eX128
eX256
Capacity
System Gates
Typical Gates
3,000
2,000
6,000
4,000
12,000
8,000
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64 128 256
128 256 512
Combinatorial Cells
128 256 512
Maximum User I/Os
84 100 132
Global Clocks
Hardwired
Routed
1 11
2 22
Speed Grades*
Std. Std. Std.
Temperature Grades*
A AA
Package (by pin count)
TQFP
CSP
64, 100
49, 128
64, 100
49, 128
100
128, 180
Note: * The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to the eX
Family FPGAs datasheet for more details.
June 2006
© 2006 Actel Corporation
i
1 page  
eX Automotivewww.DataSheet4U.com Family FPGAs
eX Automotive Family FPGAs
General Description
Based on a 0.22 µm CMOS process technology, the eX
family of FPGAs is a low-cost solution for low-power,
high-performance designs. With the automotive
temperature grade support (–40ºC to 125ºC), the eX
devices can address many in-cabin telematics and
automobile interconnect applications. The low-power
attributes inherent in antifuse technology make the eX
devices ideal for designers who are looking to integrate
low-density, power-sensitive automotive applications
into a programmable logic solution, enabling quick time-
to-market.
eX Family Architecture
The Actel eX family is implemented on a high-voltage
twin-well CMOS process using 0.22 µm design rules. The
eX family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a
grid of logic modules with virtually no chip area lost to
interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
patented metal-to-metal programmable antifuse
interconnect elements. The antifuse interconnect is
made up of a combination of amorphous silicon and
dielectric material with barrier metals and has an "on"
state resistance of 25 Ω with a capacitance of 1.0 fF for
low-signal impedance. The antifuses are normally open
circuit and, when programmed, form a permanent low-
impedance connection. Actel’s eX family provides two
types of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-1). The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the eX FPGA. The clock source for the R-
cell can be chosen from either the hardwired clock or the
routed clock.
The C-cell implements a range of combinatorial functions
up to five inputs (Figure 1-2 on page 1-2). Inclusion of
the DB input and its associated inverter function enables
the implementation of more than 4,000 combinatorial
functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-
flop to imitate an R-cell via the use of the CC macro. This
is particularly useful when implementing nontiming-
critical paths and when the design engineer is running
out of R-cells. For more information about the CC macro,
refer to the Actel Maximizing Logic Utilization in eX, SX
and SX-A FPGA Devices Using CC Macros application
note.
Routed
Data Input S1
S0
DirectConnect
Input
PSET
DQ
Y
Figure 1-1 • R-Cell
HCLK
CLKA,
CLKB,
Internal Logic
CKS
CLR
CKP
v3.2
1-1
5 Page 
eX Automotive Family FPGAs
www.DataSheet4U.com
180
160
140
120
100
80
60
40
20
0
0 25 50 75 100 125 150 175 200
Frequency (MHz)
Figure 1-10 • Total Dynamic Power (mW)
32-bit Decoder
8 x 8-bit Counters
SDRAM Controller
12
10
8
5% DC
6 10% DC
15% DC
4
2
0
0 10 20 30 40 50 60
Frequency (MHz)
Figure 1-11 • System Power at 5%, 10%, and 15% Duty Cycle
v3.2
1-7
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EX128-FTQ100.PDF ] | |
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