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PDF TM-1100 Data sheet ( Hoja de datos )
| Número de pieza | TM-1100 | |
| Descripción | Programmable Media Processor | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Programmable Media Processor
FEATURES
+ Processes audio, video, graphics and communications
datastreams on a single chip
+ Powerful, fine-grain parallel, 133-MHz VLIW CPU with
versatile instruction set includes special multimedia and
DSP operations
+ Pin compatibility with TM-1000 delivers up to 33%
more performance to TriMedia TM-1000 designs
+ Multiple, independent, DMA-driven multimedia I/O and
coprocessing units format data and offload the CPU
+ Enhanced video out functionality includes 7-bit alpha
blending, full chroma keying, genlock capability, and
programmable YUV color clipping
+ PCI/XIO bus interface supports glueless interface to a
mix of PCI and 8-bit microcomputer peripheral chips,
such as ROM/Flash, EEPROM, 68K, and x86 devices
+ Robust software development tools enable multimedia
application development entirely in C/C++
+ DVD playback authentication/descrambling functions
for PC and standalone applications
+ 16- and 64-Mbit SDRAM support up to 133-MHz
TriMedia TM-1100
O n a s i n g l e c h i p , a Tr i Me d i a™ T M - 1 1 0 0 d e l i ve r s
real-time processing of audio, video, graphics,
and communications datastreams. With its low-
cost 133-MHz CPU and a full complement of
on-chip I/O and coprocessing peripheral units,
the TM-1100 media processor delivers up to
5.3 BOPS to new multimedia products. 100%
pin compatibility with the TM-1000 processor
ensures that developers can take immediate
advantage of up to 33% more processing power
in their existing TM-1000 designs.
Comparable in programmability to a general-
p u r p o s e p r o c e s s o r, t h e Tr i Me d i a T M - 1 1 0 0
architecture enables development of multi-
media applications entirely in the C and C++
programming languages. Programmability
improves time-to-market, lowers development
costs, and extends product life through
software upgradability.
MULTIMEDIA APPLICATIONS
The TM-1100 is an ideal building block for any multimedia appli-
cation that processes multiple multimedia and communications
datastreams. It is well suited for creating a range of consumer and
professional products such as videophones, videoconferencing and
video editing systems, security systems, DVD encode/decode
devices, and digital television appliances.
SINGLE-CHIP MULTIMEDIA ENGINE
Powered by a low-cost, 133-MHz, C-programmable CPU, the
TriMedia TM-1100 strikes a perfect compromise between cost and
performance. To streamline data throughput, TM-1100 incorporates
independent on-chip DMA-driven peripheral units that manage
datastream I/O and formatting and accelerate processing of key
multimedia algorithms. To reap the full benefit of the CPU and pro-
cessing units, TM-1100’s sophisticated memory hierarchy manages
internal I/O and streamlines access to external memory. The result —
a single, low-cost programmable chip that powers standalone and
PC-hosted multimedia products.
1 page  
internal I/O requirements of its target applications, the TM-1100
couples substantial on-chip caches with a glueless memory interface.
Dedicated instruction and data cache — TM-1100’s CPU is
supported by separate, dedicated on-chip data and instruction caches.
Even without a second-level cache structure, TriMedia caches deliver
media performance an order of magnitude greater than x86 processors.
The dual-ported data cache allows two simultaneous accesses. It is
non-blocking, thus cache misses and CPU cache accesses can be han-
dled simultaneously. Early restart techniques reduce read-miss latency.
Background copyback reduces CPU stalls.
To reduce internal bus bandwidth requirements, instructions in main
memory and cache use a compressed format. The compressed instruc-
tion format improves the cache hit rate and reduces bus bandwidth.
Instructions are compressed during compilation and decompressed in
the instruction cache before being processed by the CPU.
To improve cache behavior and thus performance, both caches have
a locking mechanism. Cache coherency is maintained by software.
Glueless memory system interface — TM-1100’s glueless main
memory interface couples the on-chip caches and multimedia
peripheral units to main memory (SDRAM). It acts as the SDRAM
controller and programmable central arbiter that allocates SDRAM
memory bandwidth for on-chip peripheral unit activities. Higher
HOST-ASSISTED COPROCESSOR
SDRAM
CAMERA
AUDIO
PCI/XIO BUS
VCR
TV MONITOR
AUDIO
GRAPHICS
CARD
RGB IMAGE SEQUENCES
HOST CPU
MEMORY
STANDALONE
SDRAM
CAMERA
AUDIO
VCR
TV MONITOR
AUDIO
PERIPHERAL PERIPHERAL
PCI/XIO BUS
ROM/FLASH
BUS
ARBITER
TM-1100 is designed for use as a coprocessor in a PC-hosted
environment or as the sole CPU in standalone systems.
UME8UU: SUM OF ABSOLUTE VALUES
OF UNSIGNED 8-BIT DIFFERENCES
SOURCE REGISTER 1
31 0
SOURCE REGISTER 2
31 0
AB CD
E F GH
|A-E| + |B-F| + |C-G| + |D-H|
DSPALU
FUNCTIONAL
UNIT
31
RESULT
0
DESTINATION
REGISTER
SPECIAL MULTIMEDIA OPERATIONS
The ume8uu operation, commonly used for motion estimation in
video compression, implements 11 simple operations in one
TriMedia special op.
bandwidth SDRAM permits TM-1100 to use a narrower and simpler
interface than would be required to achieve similar performance with
standard DRAM.
The TM-1100 memory interface provides sufficient capacity to drive
a memory system consisting of up to 133-MHz, 8-MB (four 2Mx8)
or 16-MB (two 2Mx32) SDRAMs. Larger memories can be imple-
mented by using lower memory system clock frequencies or external
buffers. Programmable speed ratios allow SDRAM to have a different
clock speed than the TM-1100 CPU. Support for a variety of memory
types, speeds, bus widths, and off-chip bank sizes allow a range of
TM-1100-based systems to be configured.
HIGH-SPEED INTERNAL BUS (DATA HIGHWAY)
The memory system interface also mediates bandwidth allocation of
the TM-1100’s on-chip central data highway. A high-speed internal
bus consisting of separate 32-bit address and data buses, the data high-
way connects the CPU and all on-chip I/O and coprocessing units to
external SDRAM (through the memory interface) and to an off-chip
PCI or XIO bus (through the PCI/XIO interface). Programmable
bandwidth enables the data highway to deliver real-time responsive-
ness in a variety of multimedia applications.
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet TM-1100.PDF ] | |
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