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TP0604 반도체 회로 부품 판매점

P-Channel Enhancement-Mode Vertical DMOS FETs



Supertex  Inc 로고
Supertex Inc
TP0604 데이터시트, 핀배열, 회로
Supertex inc.
TP0604
P-Channel Enhancement-Mode
Vertical DMOS FET
Features
Low threshold (-2.4V max.)
High input impedance
Low input capacitance (95pF typical)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Ordering Information
Product Summary
Part Number
TP0604N3-G
TP0604N3-G P002
Package Option
3-Lead TO-92
Packing
1000/Bag
BVDSS/BVDGS
(V)
-40
RDS(ON)
(max) (Ω)
2.0
ID(ON)
(min) (A)
-2.0
VGS(th)
(max) (V)
-2.4
TP0604N3-G P003
TP0604N3-G P005 3-Lead TO-92
2000/Reel Pin Configuration
TP0604N3-G P013
TP0604N3-G P014
TP2404NW
Die in wafer form
---
TP2404NJ
Die on adhesive tape ---
TP2404ND
Die in waffle pack
---
For packaged products, -G indicates package is RoHS compliant (‘Green’).
TO-92 taping specifications and winding styles per EIA-468 Standard.
Devices in Wafer / Die form are RoHS compliant (‘Green’).
Refer to Die Specification VF57 for layout and dimensions.
SOURCE
DRAIN
GATE
TO-92 (N3)
Product Marking
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Value
BVDSS
BVDGS
±20V
SiTP YY = Year Sealed
0 6 0 4 WW = Week Sealed
YYWW
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92 (N3)
Operating and storage temperature -55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Doc.# DSFP-TP0604
C082012
Supertex inc.
www.supertex.com


TP0604 데이터시트, 핀배열, 회로
TP0604
Thermal Characteristics
Package
(continIDuous)
(A)
TO-92
-0.43
Notes:
ID (continuous) is limited by max rated Tj .
ID
(pulsed)
(A)
-4.2
Power Dissipation
@TA = 25OC
(W)
0.74
θja
(OC/W)
132
IDR
(A)
-0.43
IDRM
(A)
-4.2
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
-40 - - V VGS = 0V, ID = -2.0mA
VGS(th) Gate threshold voltage
-1.0 - -2.4 V VGS = VDS, ID= -1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- -3.0 -4.5 mV/OC VGS = VDS, ID= -1.0mA
IGSS Gate body leakage
- - -100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - -10 µA VGS = 0V, VDS = Max Rating
-
-
-1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) ON-state drain current
-0.4 -0.6
-2.0 -3.3
-
-
A VGS = -5.0V, VDS = -20V
VGS = -10V, VDS = -20V
RDS(ON) Static drain-to-source on-state resistance
- 2.0 3.5
- 1.5 2.0
Ω VGS = -5.0V, ID = -250mA
VGS = -10V, ID = -1.0A
ΔRDS(ON) Change in RDS(ON) with temperature
- - 1.2 %/OC VGS = -10V, ID = -1.0A
GFS Forward transductance
400 600
- mmho VDS = -20V, ID = -1.0A
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 95 150
VGS = 0V,
- 85 120 pF VDS = -20V,
- 35 60
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- 5.0 8.0
- 7.0 18
- 10 15
- 6.0 19
VDD = -20V,
ns ID = -1.0A,
RGEN = 25Ω
VSD Diode forward voltage drop
- -1.3 -2.0
V VGS = 0V, ISD = -1.5A
trr Reverse recovery time
- 300 -
ns VGS = 0V, ISD = -1.5A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulsed test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
0V
10%
INPUT
-10V
t(ON)
90%
t(OFF)
td(ON)
tr
td(OFF)
tf
0V
OUTPUT
VDD
Doc.# DSFP-TP0604
C082012
10%
90%
90%
10%
2
Pulse
Generator
RGEN
INPUT
D.U.T.
OUTPUT
RL
VDD
Supertex inc.
www.supertex.com




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