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PDF TQ2061 Data sheet ( Hoja de datos )

Número de pieza TQ2061
Descripción High-Frequency Clock Generator
Fabricantes TriQuint Semiconductor 
Logotipo TriQuint Semiconductor Logotipo



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No Preview Available ! TQ2061 Hoja de datos, Descripción, Manual

TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Pinout Diagram
11 10 9 8 7 6 5
TQ2061
High-Frequency
Clock Generator
VDD 12
NC 13
TEST1 14
TEST2 15
NC 16
NC 17
GND 18
Phase
VCO
÷20
MUX
4 NC
3 NC
Control
MUX
2 NC
1 NC
28 NC
27 NC
26
19 20 21 22 23 24 25
TriQuint’s TQ2061 is a high-frequency clock generator. It utilizes a 25 MHz
to 35 MHz TTL input to generate a 500 MHz to 700 MHz PECL output. The
TQ2061 has a completely self-contained Phase-Locked Loop (PLL) running
at 500 MHz to 700 MHz. This stable PLL allows for a low period-to-period
output jitter of 70 ps (max), and enables tight duty cycle control of 55% to
45% (worst case).
The TQ2061 provides optional 200-ohm on-chip pull-down resistors which
are useful if the output is AC-coupled to the device being driven. In order
to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN),
and pin 23 (PDR1) should be connected to pin 22 (Q).
Features
Output frequency range:
500 MHz to 700 MHz
One differential PECL output:
600 mV (min) swing
Common-mode voltage:
VDD –1.2 V (max),
VDD –1.6 V (min)
Period-to-period output jitter:
25 ps peak-to-peak (typ)
70 ps peak-to-peak (max)
Reference clock input:
25 MHz to 35 MHz TTL-level
crystal oscillator
Self-contained loop filter
Optional 200 pull-down
resistors for AC-coupled outputs
+5 V power supply
28-pin J-lead surface-mount
package
Ideal for designs based on DEC
Alpha AXPprocessors
Various test modes on the chip simplify debug and testing of systems by
slowing the clock output or by bypassing the PLL.
For additional information and latest specifications, see our website: www.triquint.com
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TQ2061 pdf
TQ2061
Figure 6. 28-Pin MQuad J-Leaded Package Mechanical Specification
.045
X 45°
.490 ±.005
.445 ±.005
.132 ±.005
0.125
VENT PLUG
8
PIN 1
22
.490
±.005
.445
±.005
15
.015
X 45°
(All dimensions in inches)
.050 TYP.
NON-ACCUM.
.445 .028
±.005
.104
±.005
.172 ±.005
.040 MIN
.410
.018 ±.015
.050 TYP.
.060
Table 6. 28-Pin MQuad Pin Description
Pin # Pin Name
1 NC
2 NC
3 NC
4 NC
5 NC
6 NC
7 GND
8 REFCLK
9 TESTIN
10 NC
11 GND
12 VDD
13 NC
14 TEST1
Description
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
Ground
Reference Clock
Test Input
No Connect
Logic Ground
Logic VDD (+5 V)
No Connect
Test Control 1
I/O Pin # Pin Name Description
I/O
— 15 TEST2 Test Control 2
I
16 NC
No Connect
17 NC
No Connect
O
— 18 GND Ground
— 19 EVDD VDD for ECL Output (+5 V) —
— 20 PDR2 Pull-down Resistor 2 (200 ) I
I
21 QN
Differential PECL Output (–) O
I
22 Q
Differential PECL Output (+) O
— 23 PDR1 Pull-down Resistor 1 (200 ) I
— 24 GND Ground
— 25 AGND Analog Ground
— 26 AVDD Analog VDD (+5 V)
I
27 NC
No Connect
For additional information and latest specifications, see our website: www.triquint.com
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