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Calogic LLC |
N-Channel Dual JFET
CORPORATION
U421 – U426
FEATURES
Ultra Low Input Bias Current . . . . . . . 250 Fempto Amps
• Low Operating Current
•• Tight Matching Characteristics
APPLICATIONS
Ultra Low Leakage FET Input Op Amps
• Electrometer
• Infrared Detectors
•• pH Meters
DESCRIPTION
The Calogic U421 Series are Dual N-Channel JFETs on a
monolithic structure designed specifically for very high input
impedance for differential amplification and impedance
matching. This series features ultra low input bias current
(250 fempto amps, U421) while offering high gain at low
operating currents and tight matching characteristics. These
devices are available in chip form for hybrid designs as well
as a hermetic TO-78 package.
ORDERING INFORMATION
Part Package
Temperature Range
U421-U426 TO-78 Hermetic Package -55oC to +150oC
XU421-U426 Sorted Chips in Carriers -55oC to +150oC
PIN CONFIGURATION
TO-78
CJ4
C
S2 D2
G1
G2
D1 S1
1 SOURCE 1
2 DRAIN 1
3 GATE 1
4 CASE/BODY
5 SOURCE 2
6 DRAIN 2
7 GATE 2
4
3
5
6
217
BOTTOM VIEW
CORPORATION
U421 – U426
ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise noted)
Gate-to-Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±40V
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -40V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Device(DDeirsastiepa3t.i2onm(WEa/cohCStoid1e5),0ToAC)=.
25oC
.....
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400mW
Total D(DeveircaeteD6is.0sipmaWtio/no,CTtAo=15205ooCC) . . . . . . . . . . . . . 750 mW
Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC
EELLEECCTTRRIICCAALL CCHHAARRAACCTTEERRIISSTTIICCSS ((2255ooCC Uunnlleessss ootthheerrwwiissee nnootteedd))
SYMBOL
CHARACTERISTIC
STATIC
BVGSS
BVG1G2
IGSS
Gate-Source Breakdown Voltage
Gate-Gate Breakdown Voltage
Gate Reverse Current (1)
IG Gate Operating Current (1)
VGS (off) Gate-Source Cutoff Voltage
VGS Gate-Source Voltage
IDSS Saturation Drain Current
DYNAMIC
gfs Common-Source Forward Transconductance
gos Common-Source Output Conductance
Ciss Common-Source Input Capacitance
Crss Common-Source Reverse Transfer Capacitance
gfs Common-Source Forward Transconductance
gos Common-Source Output Conductance
en Equivalent Short Circuit Input
NF Noise Figure
U421-3
U424-6
MIN TYP MAX MIN TYP MAX
-40 -60
-40 -60
±40 ±40
1.0
1.0
.25
.250
-0.4 -2.0 -0.4
-1.8
60 1000 60
3.0
3.0
0.5
-500
-2.0
-2.9
1800
300 1500 300
1500
10 10
3.0 3.0
1.5 1.5
120 350 120
350
3.0 3.0
20 70
20 70
10 10
1.0 1.0
UNIT
TEST CONDITIONS
IG = -1µA, VDS = 0
V
IG = -1µA, ID = 0, IS = 0
pA T = +25oC VGS = -20V,
nA T = +125oC VDS = 0
pA
T = +25oC VDG = 10V,
T = +125oC ID = 30µA
VDS = 10V, ID = 1nA
V
VDG = 10V, ID = 30µA
µA VDS = 10V, VGS = 0
f = 1 kHz
VDS = 10V,
VGS = 0
pF f = 1MHz
f = 1kHz
nV/ Hz
dB
VDG = 10V,
ID = 30µA
f = 10Hz
f = 1kHz
f = 10 Hz
RG = 10 MΩ
SYMBOL
CHARACTERISTIC
MATCH
| VGS1-VGS2 | Differential Gate-Source Voltage
U421,4
U422,5
U423,6
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
10 15
25 mV
| VGS1-VGS2 | Differential Gate-Source Voltage
∆T Change with Temperature (2)
10 25
40 V/ oC
CMRR
Common Mode Rejection Ratio (3) 90 95
80 90
80 90
dB
TEST CONDITIONS
VDG = 10V, ID = 30µA
VDG = 10V, ID = 30µA,
TA = -55oC, TB = 25oC,
TC = 125oC
ID = 30µA, VDG = 10 to 20 V
NOTES:
1. Approximately doubles for every 10oC increase in TA.
2. Measured at endpoints TA, TB and TC.
[ ]3. CMRR = 20log10
VDD
VGS1-VGS2
VDD = 10V.
4. Case lead not connected.
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