파트넘버.co.kr U401 데이터시트 PDF


U401 반도체 회로 부품 판매점

Dual N-Channel JFET Switch



Calogic  LLC 로고
Calogic LLC
U401 데이터시트, 핀배열, 회로
Dual N-Channel JFET Switch
CORPORATION
U401 – U406
FEATURES
Minimum System Error and Calibration
Low Drift With Temperature
Operates From Low Power Supply Voltages
•• High Output Impedance
PIN CONFIGURATION
TO-71
CJ2
S2 D2
G2
G1 D1 S1
ABSOLUTE MAXIMUM RATINGS
(TA = 25oC unless otherwise specified)
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . . 50V
Gate Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Storage Temperature Range . . . . . . . . . . . . . -65oC to +200oC
Operating Temperature Range . . . . . . . . . . . -55oC to +150oC
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC
Power Dissipation (TA = 85oC)
Derate above 25oC
One Side
300mW
2.6mW/ oC
Both Sides
500mW
5mW/ oC
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING INFORMATION
Part Package
U401-6 Hermetic TO-71
XU401-6 Sorted Chips in Carriers
Temperature Range
-55oC to +150oC
-55oC to +150oC


U401 데이터시트, 핀배열, 회로
CORPORATION
U401 – U406
ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified)
SYMBOL
BVGSS
IGSS
VGS(off)
VGS(on)
IDSS
IG
BVG1-G2
gfs
gos
gfs
gos
Ciss
Crss
en
PARAMETER
U401
U402
U403
U404
U405
U406
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
TEST CONDITIONS
Gate-Source
Breakdown Voltage
-50
-50
-50
-50
-50
-50
V VDS = 0, IG = -1µA
Gate Reverse Current
(Note 2)
-25
-25
-25
-25
-25
-25 pA VDS = 0, VGS = -30V
Gate-Source Cutoff
Voltage
Gate-Source Voltage
(on)
-.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5
-2.3 -2.3 -2.3 -2.3 -2.3 -2.3
VDS = 15V, ID = 1nA
V
VDG = 15V, ID = 200µA
Saturation Drain
Current (Note 3)
0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 mA VDS = 10V, VGS = 0
Operating Gate
Current (Note 2)
-15 -15 -15 -15 -15 -15 pA VDG = 15V, ID = 200µA
-10 -10 -10 -10 -10 -10 nA
TA = 125oC
Gate-Gate
Breakdown Voltage
±50
±50
±50
±50
±50
±50
V
VDS = 0, VGS = 0,
IG = ±1µA
Common-Source
Forward
Transconductance
(Note 3)
2000 7000 2000 7000 2000 7000 2000 7000 2000 7000 2000 7000
VDS = 10V,
VGS = 0
f = 1kHz
Common-Source
Output Conductance
20
20
20
20
20
20 µS
Common-Source
Forward
Transconductance
Common-Source
Output Conductance
1000 2000 1000 2000 1000 2000 1000 2000 1000 2000 1000 2000
2.0 2.0 2.0 2.0 2.0 2.0
f = 1kHz
VDG = 15V,
ID = 200µA
Common-Source
Input Capacitance
(Note 6)
Common-Source
Reverse Transfer
Capacitance (Note 6)
8.0 8.0 8.0 8.0 8.0 8.0
pF
3.0 3.0 3.0 3.0 3.0 3.0
f = 1MHz
Equivalent
Short-Circuit Input
Noise Voltage
20
20
20
20
20
20
nV VDS = 15V, f = 10Hz
√Hz VGS = 0
(Note 6)
CMRR
Common-Mode
Rejection Ratio
95
95
95
95
90
| VGS1 VGS2 |
Differential
Gate-Source Voltage
5
10 10 15 20
| VGS1 VGS2 |
T
Gate-Source Voltage
Differential Drift (Note
4)
10
10
25
25
40
dB
VDG = 10 to 20V,
ID = 200µA (Note 5, 6)
40 mV VDG = 10V, ID = 200µA
80
µV/ oC
VDG = 10V,
ID = 200µA
TA = -55oC
TB = +25oC
TC = +125oC
NOTES: 1. Per transistor.
2. Approximately doubles for every 10oC increase in TA.
3. Pulse test duration = 300µs; duty cycle 3%.
4. Measured at end points TA, TB, TC.
5.
CMRR
=
20
log10
 ∆
|
VDD
VGS1 VGS2
|
,
VDD
=
10V.
6. For design reference only, not 100% tested.




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