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Xicor |
X2816C
16K
X2816C
2048 x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
• 90ns Access Time
• Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• High Performance Advanced NMOS Technology
• Fast Write Cycle Times
—16 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 640ms Typical
—Effective Byte Write Cycle Time: 300µs
Typical
• DATA Polling
—Allows User to Minimize Write Cycle Time
• JEDEC Approved Byte-Wide Pinout
• High Reliability
—Endurance: 10,000 Cycles
—Data Retention: 100 Years
DESCRIPTION
The Xicor X2816C is a 2K x 8 E2PROM, fabricated with
an advanced, high performance N-channel floating gate
MOS technology. Like all Xicor Programmable nonvola-
tile memories it is a 5V only device. The X2816C
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs,
ROMs and EPROMs.
The X2816C supports a 16-byte page write operation,
typically providing a 300µs/byte write cycle, enabling the
entire memory to be written in less than 640ms. The
X2816C also features DATA Polling, a system software
support scheme used to indicate the early completion of
a write cycle.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PIN CONFIGURATION
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
PLASTIC DIP
SOIC
1 24
2 23
3 22
4 21
5 20
6 19
X2816C
7 18
8 17
9 16
10 15
11 14
12 13
VCC
A8
A9
WE
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3852 FHD F02.1
LCC
PLCC
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
A2 9
X2816C
26 NC
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13 21
14 15 16 17 18 19 20
I/O6
3852 FHD F03
©Xicor, 1995 Patents Pending
3852-1.4 3/27/96 T2/C3/D5 NS
Characteristics subject to change without notice
1
X2816C
PIN DESCRIPTIONS
Addresses (A0–A10)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
PIN NAMES
Symbol
A0–A10
I/O0–I/O7
WE
CE
OE
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3852 PGM T01
FUNCTIONAL DIAGRAM
A0–A10
ADDRESS
INPUTS
X BUFFERS
LATCHES AND
DECODER
Y BUFFERS
LATCHES AND
DECODER
16,384-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
CE
OE
WE
VCC
VSS
CONTROL
LOGIC
I/O0–I/O7
DATA INPUTS/OUTPUTS
3852 FHD F01
2
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