X25F087PI-5 반도체 회로 부품 판매점
SPI SerialFlash with Block Lock TM Protection
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 Xicor |
8K
X25F087
1024 x 8 Bit
SPI SerialFlash with Block LockTM Protection
FEATURES
• 1MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 1024 x 8 Bits
—16 Byte Small Sector Program Mode
• Low Power CMOS
—<1µA Standby Current
—<3mA Active Current during Program
—<400µA Active Current during Read
• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions
• Block Lock Protection
—Block Lock Protect 0, any 1/4, 1st 1/2, First or
Last Sector of SerialFlash Array
• Built-in Inadvertent Program Protection
—Power-Up/Power-Down Protection Circuitry
—Program Enable Latch
—Program Protect Pin
• Self-Timed Program Cycle
—5ms Program Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
• 8-Lead SOIC Package
• 8-Lead TSSOP Package
• 8-Pin Mini-DIP Package
DESCRIPTION
The X25F087 is a CMOS 8k-bit SerialFlash, internally
organized as 1024 x 8. The X25F087 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
There are eight options for programmable, nonvolatile,
Block Lock Protection available to the end user. These
options are implemented via special instructions
programmed to the part. The X25F087 also features a
PP pin that can be used for hardwire protection of the
part, disabling all programming attempts, as well as a
Program Enable Latch that must be set before a program
operation can be initiated.
The X25F087 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per sector and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SI
SO
SCK
COMMAND
DECODE
AND
CONTROL
LOGIC
CS
X
DECODE
LOGIC
DATA REGISTER
Y DECODE LOGIC
16 8
32
SERIALFLASH
ARRAY
(1024 x 8)
PP PROGRAM CONTROL LOGIC
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7007-0.7 5/8/97 T1/C0/D0 SH
1
HIGH VOLTAGE
CONTROL
7007 FRM 01
Characteristics subject to change without notice
X25F087
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses,
and data to be programmed to the memory are input on
this pin. Data is latched by the rising edge of the serial
clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25F087 is deselected and the
SO output pin is at high impedance and unless a nonvol-
atile write cycle is underway, the X25F087 will be in the
standby power mode. CS LOW enables the X25F087,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Program Protect (PP)
When PP is LOW, nonvolatile writes to the X25F087 are
disabled, but the part otherwise functions normally. When
PP is held HIGH, all functions, including nonvolatile
writes, operate normally. PP going LOW while CS is still
LOW will interrupt a programming cycle to the X25F087.
If the nonvolatile write cycle has already been initiated,
PP going low will have no affect on this cycle.
PIN CONFIGURATION
8 PIN SOIC/DIP
CS
SO
*0.197" PP
VSS
18
27
3 X25F087 6
45
VCC
NC
SCK
SI
*0.244"
8 PIN TSSOP
NC
0.122"
VCC
CS
SO
18
27
3 X25F0876
45
SCK
SI
VSS
PP
Not to scale
0.252"
*SOIC Measurement
7007 FRM 02
PIN NAMES
Symbol
Description
CS Chip Select Input
SO Serial Output
SI Serial Input
SCK
Serial Clock Input
PP Program Protect Input
VSS Ground
VCC Supply Voltage
NC No Connect
7007 FRM T01
PRINCIPLES OF OPERATION
The X25F087 is a 1024 x 8 SerialFlash designed to inter-
face directly with the synchronous Serial Peripheral Inter-
face (SPI) of many popular microcontroller families.
The X25F087 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW and the PP
input must be HIGH during the entire operation. Table 1
contains a list of the instructions and their opcodes. All
instructions, addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then start it again to resume opera-
tions where left off.
Program Enable Latch
The X25F087 contains a “Program Enable” latch. This
latch must be SET before a program operation is initi-
ated. The PREN instruction will set the latch and the
PRDI instruction will reset the latch (Figure 4). This latch
is automatically reset upon a power-up condition and
after the completion of a sector program cycle.
Block Lock Protection
There are eight Block Lock Protection options. The pre-
defined blocks and associated address ranges are pro-
tected by programming the appropriate two byte
Program Status instruction to the device (Table 1 and
Figure 6). Once a Block Lock protect instruction has
been completed, that Block Lock Protection setup is held
in a nonvolatile Status Register (Figure 1) until the next
Program Status instruction is issued. The sections of the
memory array that are Block Lock protected can be read
but not programmed until Block Lock Protection is
removed or changed.
2
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