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Xicor |
APPLICATION NOTE
AVA I L A B L E
X20C05 AN56
4K X20C05
High Speed AUTOSTORE™ NOVRAM
512 x 8
FEATURES
• Fast Access Time: 35ns, 45ns, 55ns
• High Reliability
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
• Power-on Recall
—E2PROM Data Automatically Recalled Into
SRAM Upon Power-up
• AUTOSTORE™ NOVRAM
—User Enabled Option
—Automatically Stores SRAM Data Into the
E2PROM Array When VCC Low Threshold is
Detected
—Open Drain AUTOSTORE Status Output Pin
• Software Data Protection
—Locks Out Inadvertent Store Operations
• Low Power CMOS
—Standby: 250µA
• Infinite E2PROM Array Recall, and RAM Read
and Write Cycles
• Upward compatible with X20C16 (16K)
DESCRIPTION
The Xicor X20C05 is a 512 x 8 NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a non-
volatile electrically erasable PROM (E2PROM). The
X20C05 is fabricated with advanced CMOS floating
gate technology to achieve high speed with low power
and wide power-supply margin. The X20C05 features
the JEDEC approved pinout for byte-wide memories,
compatible with industry standard RAMs, ROMs,
EPROMs, and E2PROMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 5µs or less.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, and a minimum 1,000,000 store operations to
the E2PROM. Data retention is specified to be greater
than 100 years.
PIN CONFIGURATION
PLASTIC
CERDIP
NE
NC
7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 X20C05 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
AS
A8
NC
NC
OE
NC
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3827 FHD F02
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991 - 1997 Patents Pending
3827-2.7 7/31/97 T4/C0/D0 SH
LCC
PLCC
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 NC
A4 7
27 NC
A3 8
A2 9
A1 10
X20C05
(TOP VIEW)
26 NC
25 OE
24 NC
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
3827 FHD F03
1 Characteristics subject to change without notice
X20C05
PIN DESCRIPTIONS
Addresses (A0–A8)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE, or NE.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20C05 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to the
RAM.
FUNCTIONAL DIAGRAM
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls the recall function
to the E2PROM array.
AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-
cates VCC has fallen below the AUTOSTORE threshold
(VASTH). AS may be wire-ORed with multiple open drain
outputs and used as an interrupt input to a microcontroller.
PIN NAMES
Symbol
A0–A8
I/O0–I/O7
WE
CE
OE
NE
AS
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
Nonvolatile Enable
AUTOSTORE Output
+5V
Ground
No Connect
3827 PGM T01
AS VCC SENSE
EEPROM ARRAY
A3–A6
CE
OE
WE
NE
A0–A2
A7–A8
ROW
SELECT
CONTROL
LOGIC
HIGH SPEED
512 x 8
SRAM
ARRAY
COLUMN
SELECT
&
I/OS
I/O0–I/O7
2
3827 FHD F01
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