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PDF X9521 Data sheet ( Hoja de datos )
| Número de pieza | X9521 | |
| Descripción | Dual DCP/ EEPROM Memory | |
| Fabricantes | Xicor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X9521 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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Hot Pluggable
Preliminary Information
X9521
Fiber Channel / Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
Dual DCP, EEPROM Memory
FEATURES
• Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10kΩ
—256 Tap - 100kΩ
— Non-Volatile
—Write Protect Function
• 2 kbit EEPROM Memory with Write Protect & Block
LockTM
• 2-Wire industry standard Serial Interface
—Complies to the Gigabit Interface Converter (GBIC)
specification
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
• Packages
—CSP (Chip Scale Package)
—20 Pin TSSOP
DESCRIPTION
The X9521 combines two Digitally Controlled Potentiome-
ters (DCP’s), and integrated EEPROM with Block LockTM
protection. All functions of the X9521 are accessed by an
industry standard 2-Wire serial interface.
The DCP’s of the X9521 may be utilized to control the bias
and modulation currents of the laser diode in a Fiber Optic
module. The 2 kbit integrated EEPROM may be used to
store module definition data.
The features of the X9521 are ideally suited to simplifying
the design of fiber optic modules which comply to the Giga-
bit Interface Converter (GBIC) specification. The integration
of these functions into one package significantly reduces
board area, cost and increases reliability of laser diode
modules.
BLOCK DIAGRAM
WP
SDA
SCL
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
THRESHOLD
RESET LOGIC
8
PROTECT LOGIC
CONSTAT
REGISTER
4
2 kbit
EEPROM
ARRAY
©2000 Xicor Inc., Patents Pending
REV 1.1.9 1/30/03
www.xicor.com
WIPER
COUNTER
REGISTER
7 - BIT
NONVOLATILE
MEMORY
WIPER
COUNTER
REGISTER
8 - BIT
NONVOLATILE
MEMORY
RH1
RW1
RL1
RH2
RW2
RL2
Characteristics subject to change without notice. 1 of 26
1 page  
X9521 – Preliminary Information
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9521 ini-
tiates an internal high voltage write cycle. This cycle typi-
cally requires 5 ms. During this time, no further Read or
Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set
to either 1 or 0 in this case. If the device is still busy with
the high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation,
an ACKNOWLEDGE will be returned and the host can
then proceed with a read or write operation. (Refer to Fig-
ure 5.).
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
ACK
returned?
YES
High Voltage Cycle
complete. Continue
command sequence?
NO
NO
YES
Continue normal
Read or Write
command sequence
Issue STOP
PROCEED
Figure 5. Acknowledge Polling Sequence
N RHx
WIPER
COUNTER
REGISTER
(WCR)
NON
VOLATILE
MEMORY
(NVM)
DECODER
2
1
0
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
Figure 6. DCP Internal Structure
RLx
RWx
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9521 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RHx and RLx
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(Rwx) output. Within each individual array, only one switch
may be turned on at any one time. These switches are
controlled by the Wiper Counter Register (WCR) (See
Figure 6). The WCR is a volatile register.
On power up of the X9521, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below shows
the Initial Values of the DCP WCR’s before the contents of
the NVM is loaded into the WCR.
DCP
R1 / 100 TAP
R2 / 256 TAP
Initial Values Before Recall
VL / TAP = 0
VH / TAP = 255
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
REV 1.1.9 1/30/03
www.xicor.com
Characteristics subject to change without notice. 5 of 26
5 Page 
X9521 – Preliminary Information
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
WRITE Operation
S
Address
Byte
t
a
r
t
Slave
Address
READ Operation
S
t
o
p
10 1 0 0 0 0 0
A
C
K
10100001
AA
CC
KK
Data
“Dummy” Write
Figure 15. Random EEPROM Address Read Sequence
the Device Type Identifier 1010111 or 1010010). Immedi-
ately after an operation to a DCP or CONSTAT Register is
performed, only a “Random EEPROM Read” is available.
Immediately following a “Random EEPROM Read” , a
“Current EEPROM Address Read” or “Sequential
EEPROM Read” is once again available (assuming that
no access to a DCP or CONSTAT Register occur in the
interim).
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master
issues the START condition and the Slave Address Byte,
receives an ACKNOWLEDGE, then issues an Address
Byte. This “dummy” Write operation sets the address
pointer to the address from which to begin the random
EEPROM read operation.
After the X9521 acknowledges the receipt of the Address
Byte, the master immediately issues another START con-
dition and the Slave Address Byte with the R/W bit set to
one. This is followed by an ACKNOWLEDGE from the
X9521 and then by the eight bit word. The master termi-
nates the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition
(Refer to Figure 15.).
A similar operation called “Set Current Address” also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In this
case, the device sets the address pointer to that of the
Address Byte, and then goes into standby mode after the
STOP bit. All bus activity will be ignored until another
START is detected.
Sequential EEPROM Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data Byte
is transmitted as with the other modes; however, the mas-
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
AAA
Address C C C
KKK
0 0 01
A
C Data
K (1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
Figure 16. Sequential EEPROM Read Sequence
S
t
o
p
REV 1.1.9 1/30/03
www.xicor.com
Characteristics subject to change without notice. 11 of 26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet X9521.PDF ] | |
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