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X88064PI-60 반도체 회로 부품 판매점

E2 Micro-Peripheral



Xicor 로고
Xicor
X88064PI-60 데이터시트, 핀배열, 회로
APPLICATION NOTE
A V A I LABLE
Application Brief
iAPX88/188, MCS 196, MCS51 Compatible*
64K
X88064
8192 x 8 Bit
E2 Microcontroller Peripheral
• Block Lock Write Control
—Eight 1K Byte Blocks
- Lockable Independently or in Combination
• Multiplexed Address/Data Bus
—Direct Interface to Popular Microcontrollers
• High Performance CMOS
—Fast Access Times, 60ns and 80 ns
—Low Power
- 30mA Active Maximum
- 150µA Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
DESCRIPTION
The X88064 is a high speed byte wide microperipheral
device with eight 1K byte blocks of E2PROM and can be
directly connected to industry standard high performance
microprocessors. This peripheral provides two levels of
memory write control, the standard Software Data Pro-
gram (SDP) control and Block Lock.
Block Lock provides a higher level of memory write con-
trol above SDP. This allows the software developer to
partition any or all of the eight 1K byte blocks as In-Circuit
Programmable ROM (ICPROM). Once locked, a block of
memory must first be unlocked before being written. Not
even a write operation using the SDP sequence will
change the contents of a locked block. Since a distinct, 6
byte, software command sequence locks and unlocks
the memory, the software developer has complete con-
trol of the memory contents.
ALE
A/D0–A/D7
A8–A12
L
A
T
C
H
WR
RD
PSEN
CE
WC
INTERFACE
CONTROL
BLOCK LOCK
CONTROL
LOGIC
D
E
C
O
D
E
R
INDIVIDUALLY LOCKABLE
E2 PROM
ARRAY
1Kx8 BLOCKS
SOFTWARE DATA PROTECT
(SDP)
WE
OE BUS TRANSCEIVER
POWER-ON RESET
AND VCC SENSE
A/D0–A/D7
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
* All other brand and product names may be trademarks or
registered trademarks of their respective companies.
7023-2.3 1/29/97 T0/C2/D0 SH
1
Characteristics subject to change without notice


X88064PI-60 데이터시트, 핀배열, 회로
X88064
Software Data Program Control provides a lower level of
memory write management. SDP controls write opera-
tions to the entire memory. When enabled, the host micro-
processor must send a special 3 byte command sequence
before any byte or page writes to unlocked locations in the
memory.
Pin configuration
DIP/SOIC
NC
A12
NC
NC
WC
PSEN
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1 24
2 23
3 22
4 21
5 20
6 X88064 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
WR
ALE
A8
A9
A11
RD
A10
CE
A/D7
A/D6
A/D5
7023 FRM F02
PIN NAMES
PIN NAME
PSEN
A8–A12
AD0–AD7
WR
RD
WC
CE
ALE
I/O DESCRIPTION
I Content of E2 memory can be read by lowering the PSEN and holding both RD and WR
HIGH. The device then places on the data bus (AD0–AD7) the contents of E2 memory at the
latched address.
I Non-multiplexed high-order Address Bus inputs for the upper byte of the address.
I/O Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a
HIGH to LOW transition.
I During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is
placed on the bus. The rising edge of WR latches data into the device.
I The RD input is active LOW and is used to read content of the E2 memory at the latched
address. Both PSEN an WR signals must be held HIGH during RD controlled read operation.
I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order
to disable write to the E2 memory. Taking WC HIGH prior to tBLC (100ns, the time delay from
the last write cycle to the start of internal programming cycle) will inhibit the write operation.
I The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE
HIGH to LOW transition in order to generate a valid internal device select signal. Holding this
pin HIGH and ALE LOW will place the device in standby mode.
I Address Latch Enable input is used to latch the addresses present on the address lines
A8–A12 and AD0–AD7 into the device. The addresses are latched when ALE transitions from
HIGH to LOW.
2




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