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ZL30100 반도체 회로 부품 판매점

T1/E1 System Synchronizer



Zarlink Semiconductor Inc 로고
Zarlink Semiconductor Inc
ZL30100 데이터시트, 핀배열, 회로
ZL30100
T1/E1 System Synchronizer
Data Sheet
Features
October 2004
• Supports Telcordia GR-1244-CORE Stratum 4 and
Stratum 4E
Ordering Information
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and
1544 kbit/s interfaces
ZL30100QDC 64 pin TQFP
• Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
-40°C to +85°C
• Simple hardware control interface
• Accepts two input references and synchronizes to
any combination of 8 kHz, 1.544 MHz, 2.048 MHz,
8.192 MHz or 16.384 MHz inputs
• Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 16.384 MHz and either 4.096 MHz and
8.192 MHz or 32.768 MHz and 65.536 MHz
• Provides 5 styles of 8 kHz framing pulses
• Holdover frequency accuracy of 1.5 x 10-7
Applications
• Synchronization and timing control for multi-trunk
DS1/E1 systems such as DSLAMs, gateways and
PBXs
• Clock and frame pulse source for ST-BUS, GCI
and other time division multiplex (TDM) buses
• Line Card synchronization for PDH systems
• Lock, Holdover and selectable Out of Range
indication
• Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
• Less than 0.6 nspp intrinsic jitter on all output clocks
• External master clock source: clock oscillator or
crystal
REF0
REF1
REF_FAIL0
REF_FAIL1
OOR_SEL
REF_SEL
RST
OSCi OSCo TIE_CLR
BW_SEL LOCK OUT_SEL
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Feedback
Frequency
Select
MUX
DS1
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
TRST
MODE_SEL1:0 HMS HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.


ZL30100 데이터시트, 핀배열, 회로
ZL30100
Data Sheet
Description
The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing
and synchronization for multi-trunk T1 and E1 transmission equipment.
The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two
input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by
maintaining stable output clocks during reference switching operations and during short periods when a
reference is unavailable.
The ZL30100 is intended to be the central timing and synchronization resource for network equipment that
complies with Telcordia, ETSI, ITU-T and ANSI network specifications.
2
Zarlink Semiconductor Inc.




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