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PDF Z53C80 Data sheet ( Hoja de datos )
| Número de pieza | Z53C80 | |
| Descripción | SMALL COMPUTER SYSTEM INTERFACE (SCSI) | |
| Fabricantes | Zilog. | |
| Logotipo |  |
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ZILOG Z53C80 SCSI
PRODUCT SPECIFICATION
FEATURES
s Pin Compatible with the Industry Standard 5380
s 44-Pin PLCC or 48-Pin DIP Package Styles
s DMA or Programmed I/O Data Transfers
s Arbitration Support
s Supports Normal or Block Mode DMA
s Memory or I/O Mapped CPU Interface
Z53C80
SMALL COMPUTER
SYSTEM INTERFACE (SCSI)
s Asynchronous Interface (Supports 3 MB/s)
s Direct SCSI Bus Interface with On-Board 48 mA Drivers
s Supports Target and Initiator Roles
s Meets SCSI Protocol as Defined in ANSI X3.131-1986
Standard
s Added “Glitch Eater” Enhancement to Minimize Bus
Reflection
GENERAL DESCRIPTION
The Z53C80 SCSI (Small Computer System Interface)
controller is designed to implement the SCSI protocol as
defined by the ANSI X3.131-1986 standard, and it is fully
compatible with the industry standard 5380. The device is
capable of operating both as a Target and as an Initiator.
Special high-current open-drain outputs enable it to directly
interface to the SCSI bus. The Z53C80 has the necessary
interface hook-ups which allow the system CPU to
communicate with it as with any other peripheral device.
The CPU can read from, or write to, the SCSI registers
which are addressed as standard or memory-mapped
I/Os.
The Z53C80 increases the system performance by
minimizing the CPU intervention in DMA operations which
the SCSI controls. The CPU is interrupted by the SCSI
when it detects a bus condition that requires attention. It
also supports arbitration and reselection. The Z53C80 has
the proper handshake signals to support normal and block
mode DMA operations with most DMA controllers available.
The added enhancement known as the “Glitch Eater” is
used to minimize effects of bus reflection on improperly
terminated SCSI bus applications. The high frequency
reflections that can occur on the SCSI bus are filtered out,
reducing the sensitivity of the inputs, specifically /REQ and
/ACK to bus signal reflections. Figure 1 shows a worst case
input waveform (labeled A), along with the filtered input
(labeled B) and the output of a Schmitt trigger used to
provide the hysteresis required on SCSI inputs (labeled
C). This enhancement is a requirement for the device to
function properly in a Apple Macintosh® environment.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
PS97SCC0200
® Apple Macintosh is a registered trademark of Apple Computer, Inc.
1
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ZILOG
PIN DESCRIPTION
Z53C80 SCSI
Microprocessor Bus
A2-A0 Address Lines (Input). Address lines are used to
access all internal registers with /CS, /IOR, and /IOW.
/CS /Chip Select (Input, active Low). /CS, in conjunction
with /RD or /WR, enables the internal register selected by
A2-A0, to be read from or write to. /CS and /DACK must
never be active simultaneously.
/DACK /DMA Acknowledge (Input, active Low). /DACK, in
conjunction with /IOR and /IOW, is used to enable reading
or writing the SCSI I/O Data Registers when in the DMA
Mode. When the DRQ has acknowledged that the byte has
been successfully transferred to or from the DMA controller,
this signal is asserted. /DACK and /CS must never be
active simultaneously.
DRQ DMA Request (Output, active High). This signal is
asserted when the chip is ready to transfer a data byte to
and from the DMA controller. The DMA Request will be
asserted only if the DMA Mode bit (Register 2, Bit 1) is set.
The transfer is complete upon reception of /DACK.
/IOR /I/O Read (Input, active Low). This signal is used to
read an internal register selected by /CS and A2-A0. The
Input Data Register can also be selected by this signal
when /DACK is active during DMA transfers.
/IOW /I/O Write (Input, active Low). This signal is used to
write to an internal register selected by /CS and A2-A0. The
Output Data Register can also be selected by this signal
when used with /DACK during DMA transfers.
IRQ Interrupt Request (Output, active High). IRQ alerts the
microprocessor of an error condition or an event completion.
Most of the interrupts are individually maskable.
READY Ready (Output, active High). This signal can be
used to control the data transfer handshaking of block
mode DMA transfers. READY is asserted to indicate that
the chip is ready to transfer data and remains false after a
transfer until the chip is ready for another DMA transfer.
READY is always asserted when the DMA Mode Bit is a
zero.
D7-D0 Data Lines (Bi-directional; Tri-State, active High).
The Data Bus lines carry data and commands to and from
SCSI. D7 is the most significant bit of this bus.
/RESET /Reset (Input, active Low). /RESET clears all
registers and has no effect upon the SCSI /RST signal.
Therefore it does not reset the SCSI bus.
/EOP /End of Process (Input, active Low). To terminate a
DMA transfer, this signal is asserted. The current byte will
be transferred but no additional bytes will be requested if
asserted during a DMA cycle. /EOP can be used to
generate an interrupt when it is received from a DMA
Controller.
PS97SCC0200
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ZILOG
Bit 7. Last Byte Sent (Read Only). The End Of DMA
Transfer bit (Bus and Status Register, bit 7) only indicates
when the last byte was received from the DMA controller.
The Last Byte Sent bit can be used to flag that the last byte
of the DMA send operation has been transferred on the
SCSI Data Bus.
Address: 3
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Assert I//O
Assert C//D
Assert /MSG
Assert /REQ
"X"
Last Byte Sent
Address: 4
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Z53C80 SCSI
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
Figure 12. Current SCSI Bus Status Register
Figure 11. Target Command Register
Address: 4
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Current SCSI Bus Status Register. Address 4 (Read
Only). The Current SCSI Bus Register is a read-only
register which is used to monitor seven SCSI Bus control
signals, plus the Data Bus parity bit. For example, an
Initiator device can use this register to determine the
current bus phase and to poll /REQ for pending data
transfers. This register may also be used to determine why
a particular interrupt occurred. Figure 12 describes the
Current SCSI Bus Status Register.
Select Enable Register. Address 4 (Write Only). The
Select Enable Register (Figure 13) is a write-only register
which is used as a mask to monitor a signal ID during a
selection attempt. The simultaneous occurrence of the
correct ID bit, /BSY FALSE, and /SEL TRUE will cause an
interrupt. This interrupt can be disabled by resetting all bits
in this register. If the Enable Parity Checking bit (Mode
Register, bit 5) is active (1), parity is checked during
selection.
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 13. Select Enable Register
PS97SCC0200
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